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1. WO2022205519 - SOURCE DRIVER CHIP AND DISPLAY APPARATUS

Publication Number WO/2022/205519
Publication Date 06.10.2022
International Application No. PCT/CN2021/087753
International Filing Date 16.04.2021
IPC
G09G 3/20 2006.1
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
CPC
G09G 2310/0275
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
2310Command of the display device
02Addressing, scanning or driving the display screen or processing steps related thereto
0264Details of driving circuits
0275Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
G09G 2310/0286
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
2310Command of the display device
02Addressing, scanning or driving the display screen or processing steps related thereto
0264Details of driving circuits
0286Details of a shift registers arranged for use in a driving circuit
G09G 2330/00
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
2330Aspects of power supply; Aspects of display protection and defect management
G09G 3/20
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix ; no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Applicants
  • TCL华星光电技术有限公司 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN]/[CN]
Inventors
  • 刘金风 LIU, Jinfeng
Agents
  • 深圳紫藤知识产权代理有限公司 PURPLEVINE INTELLECTUAL PROPERTY (SHENZHEN) CO., LTD.
Priority Data
202110332835.729.03.2021CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) SOURCE DRIVER CHIP AND DISPLAY APPARATUS
(FR) PUCE D'ATTAQUE DE SOURCE ET APPAREIL D'AFFICHAGE
(ZH) 源驱动芯片及显示装置
Abstract
(EN) Disclosed are a source driver chip (100) and a display apparatus (1000). The source driver chip (100) comprises an OR logic arithmetic unit (10), a clock buffer (20), a shift register (30) and an AND logic arithmetic unit (40). By means of an OR logic operation of a row latch signal (TP) and a first output data delay control enable signal (ODDC-EN), a second output data delay control enable signal (ODDC-ENX) is obtained, and by means of an AND logic operation of an initial row latch sub-signal (PTP1-PTP80) and the second output data delay control enable signal (ODDC-ENX), the electrostatic interference to which the row latch signal (TP) is subjected can be reduced.
(FR) L'invention concerne une puce d'attaque de source (100) et un appareil d'affichage (1000). La puce d'attaque de source (100) comprend une unité arithmétique logique OR (10), un tampon d'horloge (20), un registre à décalage (30) et une unité arithmétique logique AND (40). Au moyen d'une opération logique OR d'un signal de verrouillage de rangée (TP) et d'un premier signal de validation de commande de retard de données de sortie (ODDC-EN), un second signal de validation de commande de retard de données de sortie (ODDC-ENX) est obtenu, et au moyen d'une opération logique AND d'un sous-signal de verrouillage de rangée initial (PTP1-PTP80) et du second signal de validation de commande de retard de données de sortie (ODDC-ENX), l'interférence électrostatique à laquelle le signal de verrouillage de rangée (TP) est soumis peut être réduite.
(ZH) 公开了一种源驱动芯片(100)及显示装置(1000),源驱动芯片(100)包括或逻辑运算器(10)、时钟缓冲器(20)、移位寄存器(30)以及与逻辑运算器(40);通过行锁存信号(TP)和第一输出数据延时控制使能信号(ODDC-EN)的或逻辑运算得到第二输出数据延时控制使能信号(ODDC-ENX),以及通过初始行锁存子信号(PTP1~PTP80)和第二输出数据延时控制使能信号(ODDC-ENX)的与逻辑运算,可以降低行锁存信号(TP)受到的静电干扰。
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