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1. WO2022165479 - METADATA STORAGE AT A MEMORY DEVICE

Publication Number WO/2022/165479
Publication Date 04.08.2022
International Application No. PCT/US2022/070322
International Filing Date 24.01.2022
IPC
G06F 11/10 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 9/30 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 3/06 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from, or digital output to, record carriers
CPC
G11C 2029/0411
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
0411Online error correction
G11C 29/1201
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
1201comprising I/O circuitry
G11C 29/42
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
38Response verification devices
42using error correcting codes [ECC] or parity check
G11C 29/4401
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
44Indication or identification of errors, e.g. for repair
4401for self repair
H03K 19/1737
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
1733Controllable logic circuits
1737using multiplexers
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • SCHAEFER, Scott, E.
  • BOEHM, Aaron, P.
Agents
  • CLOUSE, Ian
Priority Data
17/648,39319.01.2022US
63/142,41327.01.2021US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) METADATA STORAGE AT A MEMORY DEVICE
(FR) STOCKAGE DE MÉTADONNÉES DANS UN DISPOSITIF DE MÉMOIRE
Abstract
(EN) Methods, systems, and devices for metadata storage at a memory device are described to support storage of metadata information and error control information at a memory device. The metadata information and error control information may be received at the memory device via a sideband channel and corresponding pin. For example, a set of bits received via the pin may include a subset of error control bits and a subset of metadata bits. Circuitry at the memory device may receive the set of bits via the pin and may identify metadata information and error control information within the set of bits. The circuitry may route the metadata information to a corresponding subset of memory cells and the error control information to an error control circuit, where the error control circuit may route the error control information to a corresponding subset of memory cells.
(FR) Des procédés, des systèmes et des dispositifs de stockage de métadonnées dans un dispositif de mémoire sont décrits pour prendre en charge le stockage d'informations de métadonnées et d'informations de contrôle d'erreur dans un dispositif de mémoire. Les informations de métadonnées et les informations de contrôle d'erreur peuvent être reçues au niveau du dispositif de mémoire par l'intermédiaire d'un canal de bande latérale et d'une broche correspondante. Par exemple, un ensemble de bits reçu par l'intermédiaire de la broche peut comprendre un sous-ensemble de bits de contrôle d'erreur et un sous-ensemble de bits de métadonnées. Un circuit au niveau du dispositif de mémoire peut recevoir l'ensemble de bits par l'intermédiaire de la broche et peut identifier des informations de métadonnées et des informations de contrôle d'erreur dans l'ensemble de bits. Le circuit peut acheminer les informations de métadonnées vers un sous-ensemble correspondant de cellules de mémoire et les informations de contrôle d'erreur vers un circuit de contrôle d'erreur, le circuit de contrôle d'erreur pouvant acheminer les informations de contrôle d'erreur vers un sous-ensemble correspondant de cellules de mémoire.
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