WO2022164602 MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS AND METHOD USED IN FORMING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS

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Publication Number WO/2022/164602

Publication Date 04.08.2022

International Application No. PCT/US2022/011014

International Filing Date 03.01.2022

IPC

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CPC

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Applicants

MICRON TECHNOLOGY, INC. [US]/[US]

Inventors

SCARBROUGH, Alyssa N.
HOPKINS, John D.

Agents

MATKIN, Mark S.

Priority Data

17/162,062

29.01.2021

Publication Language English (en)

Filing Language English (EN)

Designated States

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Title

(EN) MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS AND METHOD USED IN FORMING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS

(FR) MATRICE DE MÉMOIRE COMPRENANT DES CHAÎNES DE CELLULES DE MÉMOIRE ET PROCÉDÉS UTILISÉS POUR FORMER UNE MATRICE DE MÉMOIRE COMPRENANT DES CHAÎNES DE CELLULES DE MÉMOIRE

Abstract

(EN) A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Simultaneously, (a), (b), and (c) are formed, where (a): horizontally-elongated trenches into the stack laterally-between immediately-laterally-adjacent of the memory-block regions; (b): channel openings into the stack laterally-between the horizontally-elongated trenches; and (c): through-array-via (TAV) openings into the stack in a stair-step region. Intervening material is formed in the horizontally-elongated trenches, a channel-material string in individual of the channel openings, and conductive material in the TAV openings. Other aspects, including structure independent of method, are disclosed.

(FR) La présente invention porte sur un procédé utilisé dans la formation de matrice de mémoire qui comprend des chaînes de cellules de mémoire, consistant à former un empilement comprenant des premiers niveaux alternés verticalement et des seconds niveaux. L'empilement comprend des régions de bloc de mémoire espacées latéralement. Simultanément, (a), (b), et (c) sont formées, (a) : des tranchées allongées horizontalement dans l'empilement latéralement entre les régions de bloc de mémoire immédiatement adjacentes aux régions de bloc de mémoire; (b) : des ouvertures de canal dans l'empilement latéralement entre les tranchées allongées horizontalement; et (c) : des ouvertures de trou d'interconnexion traversant le réseau (TAV) dans l'empilement dans une région en escalier. Un matériau intermédiaire est formé dans les tranchées allongées horizontalement, une chaîne de matériau de canal dans chaque ouverture de canal, et un matériau conducteur dans les ouvertures TAV. La présente invention porte sur d'autres aspects, y compris sur une structure indépendante du procédé.

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27	Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02	including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04	the substrate being a semiconductor body
10	including a plurality of individual components in a repetitive configuration
105	including field-effect components
112	Read-only memory structures
115	Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517	with floating gate
11521	characterised by the memory core region
11524	with cell select transistors, e.g. NAND

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27	Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02	including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04	the substrate being a semiconductor body
10	including a plurality of individual components in a repetitive configuration
105	including field-effect components
112	Read-only memory structures
115	Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563	with charge-trapping gate insulators, e.g. MNOS or NROM
11568	characterised by the memory core region
1157	with cell select transistors, e.g. NAND

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27	Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02	including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04	the substrate being a semiconductor body
10	including a plurality of individual components in a repetitive configuration
105	including field-effect components
112	Read-only memory structures
115	Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517	with floating gate
11548	characterised by the boundary region between the core and peripheral circuit regions

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27	Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02	including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04	the substrate being a semiconductor body
10	including a plurality of individual components in a repetitive configuration
105	including field-effect components
112	Read-only memory structures
115	Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563	with charge-trapping gate insulators, e.g. MNOS or NROM
11575	characterised by the boundary region between the core and peripheral circuit regions

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27	Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02	including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04	the substrate being a semiconductor body
10	including a plurality of individual components in a repetitive configuration
105	including field-effect components
112	Read-only memory structures
115	Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517	with floating gate
11551	characterised by three-dimensional arrangements, e.g. with cells on different height levels
11553	with source and drain on different levels, e.g. with sloping channels
11556	the channels comprising vertical portions, e.g. U-shaped channels

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1. WO2022164602 - MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS AND METHOD USED IN FORMING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
5	Details of stores covered by G11C11/00
06	Arrangements for interconnecting storage elements electrically, e.g. by wiring

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21	Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02	Manufacture or treatment of semiconductor devices or of parts thereof
04	the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48	Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814	Conductive parts
4846	Leads on or in insulating or insulated substrates, e.g. metallisation
486	Via connections through the substrate with or without pins

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21	Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02	Manufacture or treatment of semiconductor devices or of parts thereof
04	the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48	Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814	Conductive parts
4846	Leads on or in insulating or insulated substrates, e.g. metallisation
486	Via connections through the substrate with or without pins