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1. WO2022164317 - INTEGRATED CIRCUIT, ATTACHING A DIE TO A SUBSTRATE IN AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF ADAPTING AN ATTACHMENT LAYER

Publication Number WO/2022/164317
Publication Date 04.08.2022
International Application No. PCT/NL2022/050040
International Filing Date 26.01.2022
IPC
H01L 23/488 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
H01L 21/60 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/367 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367Cooling facilitated by shape of device
H01L 23/373 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
373Cooling facilitated by selection of materials for the device
CPC
H01L 2224/2732
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
27Manufacturing methods
273by local deposition of the material of the layer connector
2731in liquid form
2732Screen printing, i.e. using a stencil
H01L 2224/27334
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
27Manufacturing methods
273by local deposition of the material of the layer connector
2733in solid form
27334using preformed layer
H01L 2224/279
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
27Manufacturing methods
279Methods of manufacturing layer connectors involving a specific sequence of method steps
H01L 2224/29011
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
2901Shape
29011comprising apertures or cavities
H01L 2224/29012
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
2901Shape
29012in top view
H01L 2224/29076
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
29075Plural core members
29076being mutually engaged together, e.g. through inserts
Applicants
  • STICHTING CHIP INTEGRATION TECHNOLOGY CENTER [NL]/[NL]
  • NEDERLANDSE ORGANISATIE VOOR TOEGEPAST-NATUURWETENSCHAPPELIJK ONDERZOEK TNO [NL]/[NL]
Inventors
  • DORRESTEIN, Sander
Agents
  • VAN DER MAARL, Arjan
Priority Data
202746329.01.2021NL
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) INTEGRATED CIRCUIT, ATTACHING A DIE TO A SUBSTRATE IN AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF ADAPTING AN ATTACHMENT LAYER
(FR) CIRCUIT INTÉGRÉ
Abstract
(EN) An integrated circuit comprises: a die (30) having a first elastic modulus (a Young's modulus, a bulk modulus, or a volumetric elasticity) and a first coefficient of thermal expansion, comprising an electronic circuit and generating heat in use; a substrate (10) having a second elastic modulus and a second coefficient of thermal expansion, for dissipating heat from the die (30); an attachment layer (20) arranged between the die (30) and the substrate (10); wherein the attachment layer (20) comprises: an attachment material (22), having a third elastic modulus and a third coefficient of thermal expansion, and a mesh (21) with openings, having a fourth elastic modulus and a fourth coefficient of thermal expansion, wherein the attachment material (22) substantially fills the openings of the mesh (21); wherein the third elastic modulus is lower than the fourth elastic modulus; wherein the attachment layer (20) has a combined fifth coefficient of thermal expansion, which is below the first coefficient of thermal expansion. The combined fifth coefficient of thermal expansion may be between the first coefficient of thermal expansion and the second coefficient of thermal expansion. The attachment layer (20) may have a combined fifth elastic modulus, being lower than the fourth elastic modulus. The combined fifth elastic modulus may be in a range between the third elastic modulus and the fourth elastic modulus, for example, the fifth elastic modulus may depend on the weight and/or the volume of the attachment material (22) relative to the weight and/or the volume of the mesh (21). The mesh (21) may be a wire mesh, such as a net or netting, intertwined structure and/or network structure. The mesh (21) may be partly or fully embedded in the attachment material (22). The mesh (21) may be in physical contact with the substrate (10). The mesh (21) may be an integrated part of the substrate (10), preferably wherein the mesh (21) is formed from protruding parts of the substrate (10) after removing, such as galvanically growing, milling or etching away, parts of the substrate (10). The mesh (21) may extend beyond a die attachment surface facing the attachment. The mesh (21) may be smaller than the die attachment surface, preferably forming a region and/or an island where the combined fifth coefficient of thermal expansion is locally adapted and/or the combined fifth elastic modulus is locally adapted, advantageously allowing the mesh (21) and/or the attachment layer (20) as a whole to be adapted to the expected amount of heat generated at a particular location in the die (30), more specific to a hot spot of the die (30). The mesh (21) may comprise mechanical parts, such as springs and/or hinges, configured for recovering its original shape when released after deformation and/or reinforcements for relieving and/or reducing thermal expansion tension in the attachment layer (20). The mesh (21) may comprise one or more of copper, nickel, tungsten, tungsten copper alloy, CuW, iron, FeNi, molybdenum and polyimide, or an alloy one or more of the previously mentioned materials. The mesh (21) is designed by identifying the hot spot location of a hot spot of the die (30); and adapting the mesh (21) based on the hot spot location. The adapting may comprise: shrinking the opening area of the mesh (21) relative to the area of the mesh (21) when projected from above at the location of the hot spot; and/or enlarging the opening area of the mesh (21) relative to the area of the mesh (21) when projected from above at the location away from the hot spot. The die (30) may have an operational die temperature, wherein the method for manufacturing the integrated circuit may comprise curing the attachment layer (20) after arranging the die (10) on top of the attachment layer (20), wherein the curing is performed at a curing temperature between the operational temperature and room temperature. The attachment layer (20) may be provided on top of the substrate (10). Providing the attachment layer (20) may comprise: applying a first layer of attachment material (22) on the substrate (10), preferably with stencil printing; placing the mesh (21) on top of the first layer, preferably pressing the mesh (21) into the first layer; and applying a second layer of attachment material (22) on the first layer and/or the mesh (21), preferably with stencil printing. Alternatively, the attachment layer (20) may be pre-produced, such as a preform of die attach material. The preform of die attach material may be manufactured by applying a first layer of attachment material (22) on a temporal surface, preferably with stencil printing; placing the mesh (21) with openings on top of the first layer (22), preferably pressing the mesh (21) into the first layer (22); applying a second layer of attachment material (22) on the first layer and/or the mesh (21), preferably with stencil printing; and preferably removing the first layer, the mesh (21), and the second layer from the temporal surface for obtaining the preform.
(FR) L'invention concerne un circuit intégré comprenant : une puce (30) ayant un premier module élastique et un premier coefficient de dilatation thermique, comprenant un circuit électronique et générant de la chaleur lors de l'utilisation; un substrat (10) ayant un deuxième module élastique et un second coefficient de dilatation thermique, et permettant de dissiper la chaleur émanant de la puce; une couche de fixation (20) disposée entre la puce et le substrat; la couche de fixation comprenant : une maille (21) comportant des ouvertures, et ayant un quatrième module élastique; et un matériau de fixation (22) ayant un troisième module élastique, et remplissant sensiblement les ouvertures de la maille; le troisième module élastique étant inférieur au quatrième module élastique.
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