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1. WO2022164279 - SEMICONDUCTOR PACKAGE

Publication Number WO/2022/164279
Publication Date 04.08.2022
International Application No. PCT/KR2022/001651
International Filing Date 28.01.2022
IPC
H05K 3/24 2006.1
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
22Secondary treatment of printed circuits
24Reinforcing of the conductive pattern
H05K 1/11 2006.1
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
11Printed elements for providing electric connections to or between printed circuits
H01L 23/12 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
H01L 23/48 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
CPC
H01L 23/12
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
H01L 23/48
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
H05K 1/11
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
11Printed elements for providing electric connections to or between printed circuits
H05K 1/111
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
11Printed elements for providing electric connections to or between printed circuits
111Pads for surface mounting, e.g. lay-out
H05K 1/115
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
11Printed elements for providing electric connections to or between printed circuits
115Via connections; Lands around holes or via connections
H05K 3/24
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
22Secondary treatment of printed circuits
24Reinforcing the conductive pattern
Applicants
  • 엘지이노텍 주식회사 LG INNOTEK CO., LTD. [KR]/[KR]
Inventors
  • 김홍익 KIM, Hong Ik
  • 정동헌 JOUNG, Dong Hun
  • 이충기 LEE, Chung Gi
Agents
  • 허용록 HAW, Yong Noke
Priority Data
10-2021-001392101.02.2021KR
Publication Language Korean (ko)
Filing Language Korean (KO)
Designated States
Title
(EN) SEMICONDUCTOR PACKAGE
(FR) BOÎTIER DE SEMI-CONDUCTEUR
(KO) 반도체 패키지
Abstract
(EN) A semiconductor package according to an embodiment comprises: an insulating layer; a first metal layer penetrating the upper surface and lower surface of the insulating layer; and a second metal layer arranged on the first metal layer, wherein the first metal layer comprises recessed upper surfaces and lower surfaces, the second metal layer comprises protruding lower surfaces corresponding to the recessed upper surfaces of the first metal layer, and a first height between the protruding lower surfaces of the second metal layer and the lower surface of the insulating layer is smaller than a second height between the upper surface of the insulating layer and the lower surface of the insulating layer.
(FR) Un boîtier de semi-conducteur selon un mode de réalisation comprend : une couche isolante ; une première couche métallique pénétrant la surface supérieure et la surface inférieure de la couche isolante ; et une seconde couche métallique placée sur la première couche métallique, la première couche métallique comprenant des surfaces supérieures et des surfaces inférieures évidées, la seconde couche métallique comprenant des surfaces inférieures en saillie correspondant aux surfaces supérieures évidées de la première couche métallique, et une première hauteur entre les surfaces inférieures en saillie de la seconde couche métallique et la surface inférieure de la couche isolante étant inférieure à une seconde hauteur entre la surface supérieure de la couche isolante et la surface inférieure de la couche isolante.
(KO) 실시 예에 따른 반도체 패키지는 절연층; 상기 절연층의 상면 및 하면을 관통하는 제1 금속층; 및 상기 제1 금속층 상에 배치된 제2 금속층을 포함하고, 상기 제1 금속층은 오목한 상면과 하면을 포함하고, 상기 제2 금속층은 상기 제1 금속층의 오목한 상면에 대응하는 볼록한 하면을 포함하고, 상기 제2 금속층의 볼록한 하면과 상기 절연층의 하면 사이의 제1 높이는 상기 절연층의 상면과 상기 절연층의 하면 사이의 제2 높이보다 작다.
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