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1. WO2022115366 - AUTOMATED TRANSLATION OF DESIGN SPECIFICATIONS OF ELECTRONIC CIRCUITS

Publication Number WO/2022/115366
Publication Date 02.06.2022
International Application No. PCT/US2021/060302
International Filing Date 22.11.2021
IPC
G06F 8/41 2018.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
8Arrangements for software engineering
40Transformation of program code
41Compilation
G06F 8/30 2018.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
8Arrangements for software engineering
30Creation or generation of source code
G06F 11/36 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
36Preventing errors by testing or debugging of software
G06F 30/327 2020.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design
30Circuit design
32Circuit design at the digital level
327Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 40/205 2020.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
40Handling natural language data
20Natural language analysis
205Parsing
H01L 27/02 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
CPC
G01R 31/31704
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
31704Design for test; Design verification
G06F 11/3608
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
36Preventing errors by testing or debugging software
3604Software analysis for verifying properties of programs
3608using formal methods, e.g. model checking, abstract interpretation
G06F 18/214
G06F 18/2431
G06F 18/24323
G06F 30/327
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
32Circuit design at the digital level
327Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Applicants
  • SYNOPSYS, INC. [US]/[US]
Inventors
  • PARTHASARATHY, Ganapathy
  • NANDA, Saurav
  • CHOUDHARY, Parivesh
  • PATIL, Pawan
  • VENKATACHAR, Arun
Agents
  • AHN, Dohyun
  • PANWAR, Rajendra, B.
  • PATEL, Rajiv, P.
  • KINA, Jorge, A.
  • CHENG, Hanchel
  • FARN, Michael, W.
Priority Data
17/526,68715.11.2021US
63/119,52330.11.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) AUTOMATED TRANSLATION OF DESIGN SPECIFICATIONS OF ELECTRONIC CIRCUITS
(FR) TRADUCTION AUTOMATISÉE DE SPÉCIFICATIONS DE CONCEPTION DE CIRCUITS ÉLECTRONIQUES
Abstract
(EN) Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target sentence, and generates a probabilistic shift-reduce schedule for the generated parse tree. Using the generated probabilistic shift-reduce schedule and optionally the generated parse tree, the system generates code for verifying the condition specified in the target sentence. In some embodiments, to generate the code, the system parses the target sentence using the generated probabilistic shift-reduce schedule.
(FR) Selon des modes de réalisation, l'invention concerne un système pour traduire des spécifications de conception d'un circuit électronique. Dans un mode de réalisation, la spécification de conception subit une analyse syntaxique pour identifier une ou plusieurs phrases. À partir de la ou des phrases identifiées, le système extrait des concepts sémantiques. De plus, pour chaque phrase de la ou des phrases identifiées, le système détermine si la phrase peut être traduite. Si une phrase cible peut être traduite, le système produit un arbre d'analyse syntaxique pour la phrase cible, et produit un programme de réduction-décalage probabiliste pour l'arbre d'analyse syntaxique produit. En utilisant le programme de réduction-décalage probabiliste produit et facultativement l'arbre d'analyse syntaxique produit, le système produit du code pour vérifier la condition spécifiée dans la phrase cible. Dans certains modes de réalisation, pour produire le code, le système effectue l'analyse syntaxique de la phrase cible à l'aide du programme de réduction-décalage probabiliste produit.
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