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1. WO2022115141 - ENHANCED GRATING ALIGNED PATTERNING FOR EUV DIRECT PRINT PROCESSES

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Publication Number WO/2022/115141
Publication Date 02.06.2022
International Application No. PCT/US2021/051379
International Filing Date 21.09.2021
IPC
H01L 21/033 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
033comprising inorganic layers
H01L 21/768 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 21/311 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105After-treatment
311Etching the insulating layers
CPC
G03F 1/22
GPHYSICS
03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR;
1Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
22Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultra-violet [EUV] masks; Preparation thereof
G03F 1/78
GPHYSICS
03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR;
1Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
68Preparation processes not covered by groups G03F1/20 - G03F1/50
76Patterning of masks by imaging
78by charged particle beam [CPB], e.g. electron beam patterning of masks
G03F 7/70958
GPHYSICS
03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR;
7Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
70Exposure apparatus for microlithography
708Construction of apparatus, e.g. environment, hygiene aspects or materials
7095Materials, e.g. materials for housing, stage or other support having particular properties, e.g. weight, strength, conductivity, thermal expansion coefficient
70958Optical materials and coatings, e.g. with particular transmittance, reflectance
G21K 1/062
GPHYSICS
21NUCLEAR PHYSICS; NUCLEAR ENGINEERING
KTECHNIQUES FOR HANDLING PARTICLES OR IONISING RADIATION NOT OTHERWISE PROVIDED FOR; IRRADIATION DEVICES; GAMMA RAY OR X-RAY MICROSCOPES
1Arrangements for handling particles or ionising radiation, e.g. focusing or moderating
06using diffraction, refraction or reflection, e.g. monochromators
062Devices having a multilayer structure
H01L 21/0337
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
033comprising inorganic layers
0334characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
0337characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
H01L 21/31144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31144using masks
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • M BARGHI, Seyedhamed
  • KADALI, Shyam Benegal
  • PAIK, Marvin Y.
  • FANG, Sheng-Po
  • GULER, Leonard P.
  • WALLACE, Charles H.
  • JEONG, James Y.
Agents
  • BERNADICOU, Michael A.
  • BLAIR, Steven R.
  • BLANK, Eric S.
  • BRASK, Justin K.
  • COFIELD, Michael A.
  • PARKER, Wesley E.
  • RASKIN, Vladimir
  • STRAUSS, Ryan N.
  • YATES, Steven D.
Priority Data
17/107,71730.11.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) ENHANCED GRATING ALIGNED PATTERNING FOR EUV DIRECT PRINT PROCESSES
(FR) FORMATION DE MOTIFS ALIGNÉS DE RÉSEAU AMÉLIORÉ POUR DES PROCÉDÉS D'IMPRESSION DIRECTE EUV
front page image
Abstract
(EN) Embodiments disclosed herein include methods of patterning a back-end-of-line (BEOL) stack and the resulting structures. In an embodiment a method of patterning a BEOL stack comprises forming a grating over an interlayer dielectric (ILD), and forming a spacer over the grating. In an embodiment, the spacer is etch selective to the grating. In an embodiment, the method further comprises disposing a hardmask over the grating and the spacer, and patterning the hardmask to form an opening in the hardmask. In an embodiment, the method further comprises filling the opening with a plug, removing the hardmask, and etching the spacer. In an embodiment, a portion of the spacer is protected from the etch by the plug. In an embodiment, the method may further comprise removing the plug, and transferring the grating into the ILD with an etching process.
(FR) Des modes de réalisation de la présente invention comprennent des procédés de formation de motifs sur un empilement de bout en bout (BEOL) et les structures résultantes. Dans un mode de réalisation, un procédé de formation de motifs sur un empilement BEOL comprend la formation d'un réseau sur un diélectrique intercouche (ILD) et la formation d'un élément d'espacement sur le réseau. Dans un mode de réalisation, l'élément d'espacement est sélectif par gravure sur le réseau. Dans un mode de réalisation, le procédé comprend en outre la disposition d'un masque dur sur le réseau et l'élément d'espacement, et la formation de motifs sur le masque dur pour former une ouverture dans le masque dur. Dans un mode de réalisation, le procédé consiste en outre à remplir l'ouverture avec un bouchon, à retirer le masque dur et à graver l'élément d'espacement. Dans un mode de réalisation, une partie de l'élément d'espacement est protégée de la gravure par le bouchon. Dans un mode de réalisation, le procédé peut en outre comprendre le retrait du bouchon et le transfert du réseau dans l'ILD avec un procédé de gravure.
Related patent documents
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