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1. WO2022095484 - SEMICONDUCTOR STRUCTURE FORMING METHOD AND SEMICONDUCTOR STRUCTURE

Publication Number WO/2022/095484
Publication Date 12.05.2022
International Application No. PCT/CN2021/103874
International Filing Date 30.06.2021
IPC
H01L 21/768 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528Layout of the interconnection structure
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 刘志拯 LIU, ChihCheng
Agents
  • 北京名华博信知识产权代理有限公司 BOXIN CHINA INTELLECTUAL PROPERTY
Priority Data
202011233498.806.11.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) SEMICONDUCTOR STRUCTURE FORMING METHOD AND SEMICONDUCTOR STRUCTURE
(FR) PROCÉDÉ DE FORMATION DE STRUCTURE SEMI-CONDUCTRICE ET STRUCTURE SEMI-CONDUCTRICE
(ZH) 半导体结构的形成方法及半导体结构
Abstract
(EN) Embodiments of the present disclosure provide a semiconductor structure forming method and a semiconductor structure. The method comprises: providing a substrate, the substrate comprising a central area and dummy areas located on two opposite outer sides of first direction edges of the central area, and the central area comprising a forming area and cutting areas located on two opposite outer sides of second direction edges of the forming area; forming, on the substrate, multiple core columns arranged apart from each other; forming, on the substrate, an initial mask layer surrounding and covering the sidewalls of the core columns; removing the initial mask layer located in the cutting areas, to form several mask sidewall strips arranged apart from each other located in the forming area, and preserving the initial mask layer located in the dummy areas as ring-shaped sidewalls; removing the core columns located in the central area and the dummy areas; and using the mask sidewall strips as mask etching substrates to form multiple functional structures, and using the ring-shaped sidewalls as mask etching substrates to form dummy functional structures located on two sides of the multiple functional structures.
(FR) Des modes de réalisation de la présente divulgation concernent un procédé de formation de structure semi-conductrice et une structure semi-conductrice. Le procédé consiste à : fournir un substrat, le substrat comprenant une zone centrale et des zones factices situées sur deux côtés extérieurs opposés de premiers bords de direction de la zone centrale, et la zone centrale comprenant une zone de formage et des zones de coupe situées sur deux côtés extérieurs opposés de seconds bords de direction de la zone de formage ; former, sur le substrat, de multiples colonnes centrales disposées à distance les unes des autres ; former, sur le substrat, une couche de masque initiale entourant et recouvrant les parois latérales des colonnes centrales ; éliminer la couche de masque initiale située dans les zones de coupe, pour former plusieurs bandes de paroi latérale de masque disposées à distance les unes des autres et situées dans la zone de formage, et conserver la couche de masque initiale située dans les zones factices en tant que parois latérales annulaires ; éliminer les colonnes centrales situées dans la zone centrale et les zones factices ; et utiliser les bandes de paroi latérale de masque en tant que substrats de gravure de masque pour former de multiples structures fonctionnelles, et utiliser les parois latérales annulaires en tant que substrats de gravure de masque pour former des structures fonctionnelles factices situées sur deux côtés des multiples structures fonctionnelles.
(ZH) 本公开实施例提供一种半导体结构的形成方法及半导体结构,包括:提供基底,基底包括中心区和位于中心区第一方向边缘的相对两外侧的虚置区,中心区包括成型区以及位于成型区第二方向边缘的相对两外侧的裁剪区;在基底上形成多个间隔设置的芯柱;在基底上形成环绕且覆盖芯柱侧壁的初始掩膜层;去除位于裁剪区的初始掩膜层,以形成位于成型区的若干间隔设置的掩膜侧墙条,且保留位于虚置区的初始掩膜层作为环状侧墙;去除位于中心区以及虚置区的芯柱;以掩膜侧墙条为掩膜刻蚀基底,形成多个功能结构,且以环状侧墙为掩膜刻蚀基底,形成位于多个功能结构两侧的伪功能结构。
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