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1. WO2022095451 - TEST STRUCTURE AND METHOD FOR MANUFACTURING SAME

Publication Number WO/2022/095451
Publication Date 12.05.2022
International Application No. PCT/CN2021/100202
International Filing Date 15.06.2021
IPC
H01L 21/66 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
66Testing or measuring during manufacture or treatment
CPC
H01L 22/00
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
22Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
H01L 29/78
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 王翔宇 WANG, Xiangyu
  • 李宁 LI, Ning
Agents
  • 北京名华博信知识产权代理有限公司 BOXIN CHINA INTELLECTUAL PROPERTY
Priority Data
202011233637.706.11.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) TEST STRUCTURE AND METHOD FOR MANUFACTURING SAME
(FR) STRUCTURE DE TEST ET SON PROCÉDÉ DE FABRICATION
(ZH) 测试结构及其制作方法
Abstract
(EN) Provided are a test structure and a method for manufacturing same. The method for manufacturing a test structure comprises: providing a base, and forming, on the base, a gate dielectric film and a conductive film, which are sequentially stacked; at least performing patterning etching on the conductive film, so as to form a plurality of discrete gate structures, which are located on the base, wherein in the arrangement direction of the gate structures, the spacing between adjacent gate structures is less than or equal to 110 nm; forming isolation sidewalls, which are on two opposite sides of the gate structures; and using the gate structures and the isolation sidewalls as masks, and injecting dopant ions into the base, so as to form a doped region, wherein in a direction perpendicular to the surface of the base, the spacing between the doping depth of the doped region and the top face of the base is less than 10 nm.
(FR) L'invention concerne une structure de test et son procédé de fabrication. Le procédé de fabrication d'une structure de test consiste à : fournir une base, et former, sur la base, un film diélectrique de grille et un film conducteur, qui sont empilés de manière séquentielle ; au moins réaliser une gravure de motif sur le film conducteur, de manière à former une pluralité de structures de grille discrètes, qui sont situées sur la base, dans la direction d'agencement des structures de grille, l'espacement entre des structures de grille adjacentes étant inférieur ou égal à 110 nm ; former des parois latérales d'isolation, qui sont sur deux côtés opposés des structures de grille ; et utiliser des structures de grille et des parois latérales d'isolation en tant que masques, et injecter des ions dopants dans la base, de manière à former une région dopée, dans une direction perpendiculaire à la surface de la base, l'espacement entre la profondeur de dopage de la région dopée et la face supérieure de la base étant inférieur à 10 nm.
(ZH) 本公开实施例提供一种测试结构及其制作方法,测试结构的制作方法包括:提供基底,并在所述基底上形成依次层叠的栅介质膜和导电膜;至少对所述导电膜进行图案化刻蚀,以形成位于所述基底上的多个分立的栅极结构,在所述栅极结构的排列方向上,相邻所述栅极结构之间的间距小于等于110nm;形成位于所述栅极结构相对两侧的隔离侧墙;以所述栅极结构和所述隔离侧墙为掩膜,向所述基底内注入掺杂离子,形成掺杂区,在垂直于所述基底表面的方向上,所述掺杂区的掺杂深度与所述基底顶面的间距小于10nm。
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