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1. WO2022092731 - THIN FILM TRANSISTOR AND PREPARATION METHOD THEREOF

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Publication Number WO/2022/092731
Publication Date 05.05.2022
International Application No. PCT/KR2021/015009
International Filing Date 25.10.2021
IPC
H01L 29/786 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
H01L 29/12 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
12characterised by the materials of which they are formed
H01L 29/66 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
H01L 21/02 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
Applicants
  • 포항공과대학교 산학협력단 POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION [KR]/[KR]
Inventors
  • 노용영 NOH, Yongyoung
  • 리우아오 LIU, Ao
  • 주휘휘 ZHU, Huihui
Agents
  • 강일신 KANG, Il Shin
  • 백두진 BAEK, Du Jin
  • 김정연 KIM, Jung Yun
  • 유광철 YOU, Kwang Chul
  • 권성현 KWON, Sung Hyun
Priority Data
10-2020-014100728.10.2020KR
Publication Language Korean (ko)
Filing Language Korean (KO)
Designated States
Title
(EN) THIN FILM TRANSISTOR AND PREPARATION METHOD THEREOF
(FR) TRANSISTOR À COUCHES MINCES ET SON PROCÉDÉ DE PRÉPARATION
(KO) 박막 트랜지스터 및 이의 제조 방법
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Abstract
(EN) The present invention provides a thin film transistor comprising: a substrate comprising a gate electrode; a gate insulating film positioned over the entire surface of the substrate; a semiconductor layer positioned over the entire surface of the gate insulating film; and source/drain electrodes positioned on the semiconductor layer and away from each other, wherein the semiconductor layer comprises cesium tin triiodide (CsSnI3) or methylammonium tin triiodide (MASnI3) and further comprises an additive.
(FR) La présente invention concerne un transistor à couches minces comprenant : un substrat comprenant une électrode de grille ; un film d'isolation de grille positionné sur toute la surface du substrat ; une couche semi-conductrice positionnée sur toute la surface du film isolant de grille ; et des électrodes de source/drain positionnées sur la couche semi-conductrice et éloignées l'une de l'autre, la couche semi-conductrice comprenant du triiodure d'étain de césium (CsSnI3) ou du triiodure d'étain de méthylammonium (MASnI3) et comprenant en outre un additif.
(KO) 본 발명은 게이트 전극을 포함하는 기판; 상기 기판 전면에 걸쳐 위치한 게이트 절연막; 상기 게이트 절연막 상의 전면에 위치하는 반도체층; 및 상기 반도체층 상에 서로 이격되어 위치하는 소스/드레인 전극을 포함하고, 상기 반도체층은 cesium tin triiodide (CsSnI3) 또는 methylammonium tin triiodide(MASnI3)을 포함하고, 상기 반도체층은 첨가제를 더 포함하는 박막 트랜지스터를 개시한다.
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