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1. WO2022051161 - ALTERNATE PATH FOR BRANCH PREDICTION REDIRECT

Publication Number WO/2022/051161
Publication Date 10.03.2022
International Application No. PCT/US2021/047705
International Filing Date 26.08.2021
IPC
G06F 9/38 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/30 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
CPC
G06F 12/1027
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
1027using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 2212/452
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
45Caching of specific data in cache memory
452Instruction code
G06F 9/30047
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
3004to perform operations on memory
30047Prefetch instructions; cache control instructions
G06F 9/30079
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30076to perform miscellaneous control operations, e.g. NOP
30079Pipeline control instructions
G06F 9/3009
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30076to perform miscellaneous control operations, e.g. NOP
3009Thread control instructions
G06F 9/3804
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3802Instruction prefetching
3804for branches, e.g. hedging, branch folding
Applicants
  • ADVANCED MICRO DEVICES, INC. [US]/[US]
Inventors
  • MANDKE, Aparna Chandrashekhar
  • LIN, Tzu-Wei
  • NAYAK, Bhawna
  • HAVLIR, Steven, R.
  • COHEN, Robert
  • VENKATACHAR, Ashok, T.
Agents
  • SHEEHAN, Adam, D.
Priority Data
17/012,83304.09.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) ALTERNATE PATH FOR BRANCH PREDICTION REDIRECT
(FR) CHEMIN DE REMPLACEMENT POUR REDIRECTION DE PRÉDICTION DE BRANCHEMENT
Abstract
(EN) Branch prediction circuitry [215] predicts an outcome of a branch instruction. A pipeline circuitry [225, 230, 235, 231, 232, 233] processes instructions along a first path from a predicted branch of the branch instruction. The instructions along the first path are processed concurrently with processing instructions along a second path from an unpredicted branch of the branch instruction. Information representing the state of the second portion while processing the second path is stored in one or more buffers. The instructions are processed along the second path using the information stored in the buffers in response to a misprediction of the outcome of the branch instruction. In some cases, the branch prediction circuitry determines a confidence level for the predicted outcome and the instructions along the second path from the unpredicted branch are processed in response to the confidence level being below a threshold confidence.
(FR) Un circuit de prédiction de branchement [215] prédit un résultat d'une instruction de branchement. Un circuit pipeline [225, 230, 235, 231, 232, 233] traite des instructions le long d'un premier chemin à partir d'un branchement prédit de l'instruction de branchement. Les instructions le long du premier chemin sont traitées simultanément avec le traitement d'instructions le long d'un second chemin à partir d'un branchement non prédit de l'instruction de branchement. Des informations représentant l'état de la seconde partie pendant le traitement du second chemin sont stockées dans un ou plusieurs tampons. Les instructions sont traitées le long du second chemin à l'aide des informations stockées dans les tampons en réponse à une erreur de prédiction du résultat de l'instruction de branchement. Dans certains cas, le circuit de prédiction de branchement détermine un niveau de confiance pour le résultat prédit, et les instructions le long du second chemin à partir du branchement non prédit sont traitées en réponse au fait que le niveau de confiance est inférieur à un seuil de confiance.
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