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1. WO2022047586 - FLIP CHIP MICRODEVICE STRUCTURE

Publication Number WO/2022/047586
Publication Date 10.03.2022
International Application No. PCT/CA2021/051217
International Filing Date 02.09.2021
IPC
H01L 23/00 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
H01L 21/02 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/027 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
H01L 23/52 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
CPC
H01L 21/02
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/027
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
H01L 23/00
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
H01L 23/52
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
Applicants
  • VUEREAL INC. [CA]/[CA]
Inventors
  • CHAJI, Gholamreza
  • FATHI, Ehsanollah
  • SIBONI, Hossein Zamani
Agents
  • ROWAND LLP
Priority Data
63/073,55202.09.2020US
63/110,53506.11.2020US
63/133,98205.01.2021US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) FLIP CHIP MICRODEVICE STRUCTURE
(FR) STRUCTURE DE MICRODISPOSITIF À PUCE RETOURNÉE
Abstract
(EN) What is disclosed is various aspects of the structure of flip chip or lateral micro devices having protection of connections. The various aspects comprise a structural combination of functional layers such as doped or blocking layers or quantum well structure, as well as dielectric layers, VIA's, optical enhancements layers, connection pads, protective layers, masks and additional layers. In addition, methods of fabrication of microdevices have also been disclosed where in patterning has been used. The present disclosure further relates to integrating vertical microdevices into a system substrate. The system substrate can have a backplane circuit as well. The integration covers the microdevices with dielectrics and couples the backplane through a VIA.
(FR) L'invention concerne divers aspects de la structure de puce retournée ou de micro-dispositifs latéraux ayant une protection des connexions. Les divers aspects comprennent une combinaison structurale de couches fonctionnelles telles que des couches dopées ou de blocage ou une structure de puits quantique, ainsi que des couches diélectriques, des trous d'interconnexions, des couches d'amélioration optiques, des plots de connexion, des couches de protection, des masques et des couches supplémentaires. De plus, l'invention concerne des procédés de fabrication de microdispositifs dans lesquels une formation de motifs a été utilisée. La présente invention concerne en outre l'intégration de microdispositifs verticaux dans un substrat de système. Le substrat de système peut ainsi avoir un circuit de fond de panier. L'intégration recouvre les microdispositifs avec des diélectriques et couple le fond de panier à travers un trou d'interconnexion.
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