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1. WO2022047067 - THIN-FILM STORAGE TRANSISTORS IN A 3-DIMENSIONAL ARRAY OR NOR MEMORY STRINGS AND PROCESS FOR FABRICATING THE SAME

Publication Number WO/2022/047067
Publication Date 03.03.2022
International Application No. PCT/US2021/047803
International Filing Date 26.08.2021
IPC
H01L 27/115 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
H01L 21/336 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
H01L 27/11582 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
1158with source and drain on different levels, e.g. with sloping channels
11582the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/31 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
H01L 21/311 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105After-treatment
311Etching the insulating layers
CPC
H01L 27/11578
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 29/40117
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
401Multistep manufacturing processes
4011for data storage electrodes
40117the electrodes comprising a charge-trapping insulator
Applicants
  • SUNRISE MEMORY CORPORATION [US]/[US]
Inventors
  • HERNER, Scott, Brad
  • HARARI, Eli
Agents
  • KWOK, Edward, C.
  • VLP LAW GROUP, LLP
Priority Data
63/072,77131.08.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) THIN-FILM STORAGE TRANSISTORS IN A 3-DIMENSIONAL ARRAY OR NOR MEMORY STRINGS AND PROCESS FOR FABRICATING THE SAME
(FR) TRANSISTORS DE STOCKAGE À COUCHES MINCES DANS UN RÉSEAU TRIDIMENSIONNEL OU CHAÎNES DE MÉMOIRE NOR ET LEUR PROCÉDÉ DE FABRICATION
Abstract
(EN) A thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; (b) a first semiconductor layer of a first conductivity having an opening therein; (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer.
(FR) L'invention concerne un transistor de stockage à couches minces formé dans un réseau de mémoire au-dessus d'une surface plane d'un substrat semi-conducteur. Ledit transistor comprend (a) des première et seconde couches diélectriques planes, chacune étant sensiblement parallèle à la surface plane du substrat semi-conducteur; (b) une première couche semi-conductrice d'une première conductivité ayant une ouverture à l'intérieur de celle-ci; (c) des deuxième et troisième couches semi-conductrices d'un second type de conductivité opposé au premier type de conductivité, situées sur deux côtés opposés de la première couche semi-conductrice; (d) une couche de stockage de charge disposée dans l'ouverture adjacente et en contact avec la première couche semi-conductrice; et (e) un premier conducteur disposé dans l'ouverture séparée de la première couche semi-conductrice par la couche de stockage de charge.
Latest bibliographic data on file with the International Bureau