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1. WO2022047040 - SHARED ERROR CORRECTION CODE (ECC) CIRCUITRY

Publication Number WO/2022/047040
Publication Date 03.03.2022
International Application No. PCT/US2021/047766
International Filing Date 26.08.2021
IPC
G11C 29/42 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
08Functional testing, e.g. testing during refresh, power-on self testing or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing
38Response verification devices
42using error correcting codes or parity check
G11C 11/4096 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write circuits
4096Input/output data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 8/12 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
12Group selection circuits, e.g. for memory block selection, chip selection, array selection
G06F 11/10 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
CPC
G06F 11/1068
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1068in sector programmable memories, e.g. flash disk
G11C 11/409
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • KIM, Kang-Yong
  • LEE, Hyun Yoo
Agents
  • SAUNDERS, Keith W.
Priority Data
17/412,05025.08.2021US
63/071,30027.08.2020US
63/126,44316.12.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) SHARED ERROR CORRECTION CODE (ECC) CIRCUITRY
(FR) CIRCUITS DE CODE DE CORRECTION D'ERREUR (ECC) PARTAGÉS
Abstract
(EN) Described apparatuses and methods provide error correction code (ECC) circuitry (112) that is shared between two or more memory banks (404) of a memory, such as a low-power dynamic random-access memory (DRAM). A memory device (110) may include one or more dies, and a die can have multiple memory banks. The ECC circuitry can service at least two memory banks by producing ECC values (408) based on respective data (406) stored in the two memory banks. By sharing the ECC circuitry, instead of including a per-bank ECC engine, a total die area allocated to ECC functionality can be reduced. Thus, the ECC circuitry can be elevated from a one-bit ECC algorithm to a multibit ECC algorithm, which may increase data reliability. In some cases, memory architecture may operate in environments in which a masked-write command or an internal read-modify-write operation is precluded, including with shared ECC circuitry.
(FR) L'invention concerne des appareils et des procédés qui fournissent des circuits de code de correction d'erreur (ECC) (112) qui sont partagés entre au moins deux banques de mémoire (404) d'une mémoire, telle qu'une mémoire vive dynamique (DRAM) de faible puissance. Un dispositif de mémoire (110) peut comprendre une ou plusieurs puces, et une puce peut comprendre de multiples banques de mémoire. Les circuits ECC peuvent desservir au moins deux banques de mémoire par production de valeurs ECC (408) sur la base de données respectives (406) stockées dans les deux banques de mémoire. Par partage des circuits ECC, au lieu d'inclure un moteur ECC par banque, une zone de puce totale attribuée à une fonctionnalité ECC peut être réduite. Ainsi, les circuits ECC peuvent être élevés d'un algorithme ECC à un bit à un algorithme ECC à multiples bits, ce qui peut augmenter la fiabilité des données. Dans certains cas, l'architecture de mémoire peut fonctionner dans des environnements dans lesquels une commande d'écriture masquée ou une opération de lecture-modification-écriture interne est exclue, comprenant des circuits ECC partagés.
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