Processing

Please wait...

Settings

Settings

Goto Application

1. WO2022042054 - MEMORY

Publication Number WO/2022/042054
Publication Date 03.03.2022
International Application No. PCT/CN2021/104776
International Filing Date 06.07.2021
IPC
G06F 1/12 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
12Synchronisation of different clock signals
CPC
G11C 11/408
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
G11C 11/4093
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4093Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 2207/105
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
10Aspects relating to interfaces of memory device to external buses
105Aspects related to pads, pins or terminals
G11C 7/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/1063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
1063Control signal output circuits, e.g. status or busy flags, feedback command signals
G11C 7/1066
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
1066Output synchronization
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 寗树梁 NING, Shuliang
Agents
  • 上海晨皓知识产权代理事务所(普通合伙) SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP
Priority Data
202010873279.X26.08.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) MEMORY
(FR) MÉMOIRE
(ZH) 存储器
Abstract
(EN) A memory, comprising: a memory chip (100), wherein the memory chip (100) comprises at least one channel (10), and the channel (10) comprises a plurality of memory blocks (101) that are configured to alternately perform read-write operations; a command port (102), wherein the command port (102) is configured to receive a command signal at the preset edge of a command clock, and the command signal is used for controlling the read-write operations of the memory blocks (101); and a data port (103), wherein the data port (103) is configured to receive, at the preset edge of a data clock, a data signal to be written to the memory blocks (101), or transmit the data signal. The command port (102) comprises a row address port (112) and a column address port (122); the row address port (112) is used for receiving a row address signal of a position where a target memory cell is located; and the column address port (122) is used for receiving a column address signal of the position where the target memory cell is located.
(FR) L'invention concerne une mémoire, comprenant : une puce de mémoire (100), la puce de mémoire (100) comprenant au moins un canal (10) et le canal (10) comprenant une pluralité de blocs de mémoire (101) qui sont configurés pour effectuer en alternance des opérations de lecture-d'écriture ; un port de commande (102), le port de commande (102) étant configuré pour recevoir un signal de commande au niveau du bord prédéfini d'une horloge de commande et le signal de commande étant utilisé pour commander les opérations de lecture-d'écriture des blocs de mémoire (101) ; et un port de données (103), le port de données (103) étant configuré pour recevoir, au niveau du bord prédéfini d'une horloge de données, un signal de données à écrire dans les blocs de mémoire (101) ou pour transmettre le signal de données. Le port de commande (102) comprend un port d'adresse de rangée (112) et un port d'adresse de colonne (122) ; le port d'adresse de rangée (112) est utilisé pour recevoir un signal d'adresse de rangée d'une position dans laquelle se trouve une cellule de mémoire cible ; et le port d'adresse de colonne (122) est utilisé pour recevoir un signal d'adresse de colonne de la position dans laquelle se trouve la cellule de mémoire cible.
(ZH) 一种存储器,包括:存储芯片(100),存储芯片(100)包括至少一个通道(10),通道(10)包括:多个存储块(101),多个存储块(101)被配置为交替进行读写操作;命令端口(102),命令端口(102)被配置为在命令时钟的预设沿接收命令信号,命令信号用于控制存储块(101)的读写操作;数据端口(103),数据端口(103)被配置为,在数据时钟的预设沿接收待写入到存储块(101)的数据信号或者发送数据信号;命令端口(102)包括行地址端口(112)和列地址端口(122),行地址端口(112)用于接收目标存储单元所在位置的行地址信号,列地址端口(122)用于接收目标存储单元所在位置的列地址信号。
Related patent documents
EP2021859894This application is not viewable in PATENTSCOPE because the national phase entry has not been published yet or the national entry is issued from a country that does not share data with WIPO or there is a formatting issue or an unavailability of the application.
Latest bibliographic data on file with the International Bureau