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1. WO2022042021 - METHOD FOR MANUFACTURING MEMORY, AND MEMORY

Publication Number WO/2022/042021
Publication Date 03.03.2022
International Application No. PCT/CN2021/103823
International Filing Date 30.06.2021
IPC
H01L 27/108 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
CPC
H01L 27/108
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 卢经文 LU, Jingwen
Agents
  • 北京名华博信知识产权代理有限公司 BOXIN CHINA INTELLECTUAL PROPERTY
Priority Data
202010895429.731.08.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) METHOD FOR MANUFACTURING MEMORY, AND MEMORY
(FR) PROCÉDÉ DE FABRICATION DE MÉMOIRE, ET MÉMOIRE
(ZH) 一种存储器的制作方法以及存储器
Abstract
(EN) Provided is a method for manufacturing a memory, comprising: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer, and forming, on the substrate, multiple dummy bit line layers separated from each other; forming support layers filling regions between adjacent dummy bit line layers; removing the dummy bit line layers, and forming bit line spaces between adjacent support layers; forming bit line structures filling the bit line spaces, the bit line structure comprising a bit line conductive layer and a bit line insulation layer which are sequentially stacked; and removing the support layers, and forming openings between adjacent bit line layers.
(FR) L'invention concerne un procédé de fabrication d'une mémoire, comprenant les étapes suivantes : fourniture d'un substrat et formation d'une couche sacrificielle sur le substrat ; formation de motifs sur la couche sacrificielle et formation, sur le substrat, de multiples couches de lignes de bits factices séparées les unes des autres ; formation de couches de support remplissant des régions entre des couches de lignes de bits factices adjacentes ; enlèvement des couches de ligne de bits factices et la formation d'espaces de lignes de bits entre des couches de support adjacentes ; formation de structures de lignes de bits remplissant les espaces de lignes de bits, la structure de lignes de bits comprenant une couche conductrice de ligne de bits et une couche d'isolation de ligne de bits qui sont empilées séquentiellement ; et enlèvement des couches de support et la formation d'ouvertures entre des couches de lignes de bits adjacentes.
(ZH) 本公开提供一种存储器制作方法,包括:提供基底,在基底上形成牺牲层;图形化牺牲层,在基底上形成多个相互分立的伪位线层;形成支撑层,支撑层填充满相邻伪位线层之间的区域;去除伪位线层,形成位于相邻支撑层之间的位线空间;形成位线结构,位线结构填充位线空间,且位线结构包括依次堆叠的位线导电层以及位线绝缘层;去除支撑层,形成位于相邻位线层之间的开口。
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