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1. WO2022041973 - TRANSMISSION CIRCUIT, INTERFACE CIRCUIT AND MEMORY

Publication Number WO/2022/041973
Publication Date 03.03.2022
International Application No. PCT/CN2021/101365
International Filing Date 21.06.2021
IPC
G11C 11/4093 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write circuits
4093Input/output data interface arrangements, e.g. data buffers
H03M 9/00 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
9Parallel/series conversion or vice versa
CPC
G11C 11/4076
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4076Timing circuits
G11C 11/4093
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4093Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 2207/105
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
10Aspects relating to interfaces of memory device to external buses
105Aspects related to pads, pins or terminals
G11C 29/48
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
48Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
G11C 5/025
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
G11C 5/063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 林峰 LIN, Feng
Agents
  • 上海晨皓知识产权代理事务所(普通合伙) SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP
Priority Data
202010873287.426.08.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) TRANSMISSION CIRCUIT, INTERFACE CIRCUIT AND MEMORY
(FR) CIRCUIT DE TRANSMISSION, CIRCUIT D'INTERFACE ET MÉMOIRE
(ZH) 传输电路、接口电路以及存储器
Abstract
(EN) Provided are a transmission circuit, an interface circuit and a memory. The transmission circuit comprises: an upper-layer clock pad (101), which is used for transmitting a clock signal; M upper-layer data pads (102), which are used for transmitting data signals; a lower-layer clock pad (111), which is electrically connected to the upper-layer clock pad (101), wherein the area of the lower-layer clock pad (111) is less than that of the upper-layer clock pad (101); and M lower-layer data pads (112), which are electrically connected in one-to-one correspondence to the M upper-layer data pads (102), wherein the area of each lower-layer data pad (112) is less than that of each upper-layer data pad (102); the upper-layer clock pad (101) and the upper-layer data pads (102) are located in a first layer; the lower-layer clock pad (111) and the lower-layer data pads (112) are located in a second layer; a dielectric layer is arranged between the first layer and the second layer; and the first layer, the dielectric layer and the second layer are all located on the same substrate.
(FR) Un circuit de transmission, un circuit d'interface et une mémoire sont divulgués. Le circuit de transmission comprend : une plage d'horloge de couche supérieure (101), qui est utilisée pour transmettre un signal d'horloge ; M plages de données de couche supérieure (102), qui sont utilisées pour transmettre des signaux de données ; une plage d'horloge de couche inférieure (111), qui est électriquement connectée à la plage d'horloge de couche supérieure (101), la zone de la plage d'horloge de couche inférieure (111) étant inférieure à celle de la plage d'horloge de couche supérieure (101) ; et M plages de données de couche inférieure (112), qui sont électriquement connectées en correspondance biunivoque avec les M plages de données de couche supérieure (102), la zone de chaque plage de données de couche inférieure (112) étant inférieure à celle de chaque plage de données de couche supérieure (102) ; le plage d'horloge de couche supérieure (101) et les plages de données de couche supérieure (102) étant situées dans une première couche ; la plage d'horloge de couche inférieure (111) et les plages de données de couche inférieure (112) étant situées dans une seconde couche ; une couche diélectrique étant agencée entre la première couche et la seconde couche ; et la première couche, la couche diélectrique et la seconde couche étant toutes situées sur le même substrat.
(ZH) 本申请实施例提供一种传输电路、接口电路以及存储器,传输电路包括:上层时钟焊盘(101),用于传输时钟信号;M个上层数据焊盘(102),用于传输数据信号;下层时钟焊盘(111),与上层时钟焊盘(101)电连接,且下层时钟焊盘(111)的面积小于上层时钟焊盘(101)的面积;M个下层数据焊盘(112),与M个上层数据焊盘(102)一一对应的电连接,且下层数据焊盘(112)的面积小于上层数据焊盘(102)的面积;上层时钟焊盘(101)与上层数据焊盘(102)位于第一层,下层时钟焊盘(111)与下层数据焊盘(112)位于第二层,在第一层和第二层之间包括介质层,第一层、介质层、第二层均位于同一衬底上。
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