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1. WO2022041965 - TEST CIRCUIT, TEST DEVICE AND TEST METHOD THEREFOR

Publication Number WO/2022/041965
Publication Date 03.03.2022
International Application No. PCT/CN2021/100887
International Filing Date 18.06.2021
IPC
G01R 29/02 2006.1
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
29Arrangements for measuring or indicating electric quantities not covered by groups G01R19/-G01R27/135
02Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
CPC
G11C 2029/3602
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
36Data generation devices, e.g. data inverters
3602Pattern generator
G11C 29/021
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
021in voltage or current generators
G11C 29/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
10Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
G11C 29/12015
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
12015comprising clock generation or timing circuitry
G11C 29/16
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
14Implementation of control logic, e.g. test mode decoders
16using microprogrammed units, e.g. state machines
G11C 29/36
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
36Data generation devices, e.g. data inverters
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 张良 ZHANG, Liang
Agents
  • 广州华进联合专利商标代理有限公司 ADVANCE CHINA IP LAW OFFICE
Priority Data
202010892968.531.08.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) TEST CIRCUIT, TEST DEVICE AND TEST METHOD THEREFOR
(FR) CIRCUIT DE TEST, DISPOSITIF DE TEST ET PROCÉDÉ DE TEST CORRESPONDANT
(ZH) 测试电路、测试装置及其测试方法
Abstract
(EN) A test circuit (10) and a test method. The test circuit (10) comprises: a first sampling module (100), configured to receive a pulse signal to be tested and generate a first sampling signal according to the pulse signal; and a second sampling module (200), configured to receive a pulse signal and generate a second sampling signal according to the pulse signal. The second sampling signal and the first sampling signal have a phase difference, and the phase difference is equal to a pulse width of the pulse signal.
(FR) L’invention concerne un circuit de test (10) et un procédé de test. Le circuit de test (10) comprend : un premier module d'échantillonnage (100), conçu pour recevoir un signal d'impulsion à tester et générer un premier signal d'échantillonnage en fonction du signal d'impulsion ; et un second module d'échantillonnage (200), conçu pour recevoir un signal d'impulsion et générer un second signal d'échantillonnage en fonction du signal d'impulsion. Le second signal d'échantillonnage et le premier signal d'échantillonnage ont une différence de phase, et la différence de phase est égale à une largeur d'impulsion du signal d'impulsion.
(ZH) 一种测试电路(10)和测试方法,测试电路(10)包括:第一采样模块(100),用于接收待测试的脉冲信号,并根据脉冲信号生成第一采样信号;以及第二采样模块(200),用于接收脉冲信号,并根据脉冲信号生成第二采样信号;其中,第二采样信号与第一采样信号具有一相位差,相位差等于脉冲信号的脉冲宽度。
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