Processing

Please wait...

Settings

Settings

Goto Application

1. WO2022031496 - TIMING PRECISION MAINTENANCE WITH REDUCED POWER DURING SYSTEM SLEEP

Publication Number WO/2022/031496
Publication Date 10.02.2022
International Application No. PCT/US2021/043509
International Filing Date 28.07.2021
IPC
G06F 1/08 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
08Clock generators with changeable or programmable clock frequency
G06F 1/04 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
G06F 1/06 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
06Clock generators producing several clock signals
G06F 1/10 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
10Distribution of clock signals
CPC
G06F 1/32
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
H04J 3/0667
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
02Details
06Synchronising arrangements
0635Clock or time synchronisation in a network
0638Clock or time synchronisation among nodes; Internode synchronisation
0658Clock or time synchronisation among packet nodes
0661using timestamps
0667Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
H04W 52/0229
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
WWIRELESS COMMUNICATION NETWORKS
52Power management, e.g. TPC [Transmission Power Control], power saving or power classes
02Power saving arrangements
0209in terminal devices
0225using monitoring of external events, e.g. the presence of a signal
0229where the received signal is a wanted signal
H04W 56/001
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
WWIRELESS COMMUNICATION NETWORKS
56Synchronisation arrangements
001Synchronization between nodes
H04W 56/0035
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
WWIRELESS COMMUNICATION NETWORKS
56Synchronisation arrangements
0035detecting errors in frequency or phase
Applicants
  • ANALOG DEVICES, INC. [US]/[US]
Inventors
  • WARNEKE, Brett
  • NG, Gary Wayne
  • LEMKIN, Mark Alan
Agents
  • ARORA, Suneel
  • BLACK, David W., Reg. No. 42,331
  • BEEKMAN, Marvin L., Reg. No. 38,377
  • BIANCHI, Timothy E., Reg. No. 39,610
  • LANG, Allen R., Reg. 58,829
  • PERDOK, Monique M., Reg. No. 42,989
  • SCHEER, Bradley W., Reg. No. 47,059
Priority Data
17/385,53626.07.2021US
63/061,37005.08.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) TIMING PRECISION MAINTENANCE WITH REDUCED POWER DURING SYSTEM SLEEP
(FR) MAINTIEN DE PRÉCISION DU RYTHME À PUISSANCE RÉDUITE PENDANT LE SOMMEIL DU SYSTÈME
Abstract
(EN) Embodiments of the present disclosure provide systems and methods for maintaining timing precision in different operating modes of a device (e.g., a wireless node). A timing circuit may switch clock signals between two different modes (e.g., high power and low power) while preserving timing precision. In a high-power mode, the timing circuit may provide a high frequency clock signal, and in a lower-power mode, it may provide a low frequency clock signal. Moreover, the switching between the different clock signals may be synchronized to select edges of the low frequency clock signal.
(FR) Selon des modes de réalisation, la présente invention concerne des systèmes et des procédés pour maintenir la précision du rythme dans différents modes de fonctionnement d'un dispositif (par exemple, un nœud sans fil). Un circuit de cadencement peut commuter des signaux d'horloge entre deux modes différents (par exemple, haute puissance et basse puissance) tout en préservant la précision du rythme. Dans un mode haute puissance, le circuit de cadencement peut fournir un signal d'horloge à haute fréquence, et dans un mode à plus basse puissance, il peut fournir un signal d'horloge à basse fréquence. De plus, la commutation entre les différents signaux d'horloge peut être synchronisée sur des flancs sélectionnés du signal d'horloge à basse fréquence.
Related patent documents
Latest bibliographic data on file with the International Bureau