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1. WO2022029541 - SEMICONDUCTOR DEVICE

Publication Number WO/2022/029541
Publication Date 10.02.2022
International Application No. PCT/IB2021/056692
International Filing Date 26.07.2021
IPC
G06F 12/00 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G06G 7/60 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
GANALOGUE COMPUTERS
7Devices in which the computing operation is performed by varying electric or magnetic quantities
48Analogue computers for specific processes, systems, or devices, e.g. simulators
60for living beings, e.g. their nervous systems
G06N 3/063 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
G11C 5/04 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
02Disposition of storage elements, e.g. in the form of a matrix array
04Supports for storage elements; Mounting or fixing of storage elements on such supports
H01L 21/8242 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8242Dynamic random access memory structures (DRAM)
H01L 27/108 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
CPC
G06F 12/00
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G06G 7/60
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
GANALOGUE COMPUTERS
7Devices in which the computing operation is performed by varying electric or magnetic quantities
48Analogue computers for specific processes, systems or devices, e.g. simulators
60for living beings, e.g. their nervous systems ; ; for problems in the medical field
G06N 3/063
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
G11C 5/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
04Supports for storage elements ; , e.g. memory modules; Mounting or fixing of storage elements on such supports
H01L 27/108
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
Applicants
  • 株式会社半導体エネルギー研究所 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP]/[JP]
Inventors
  • 松嵜隆徳 MATSUZAKI, Takanori
  • 大貫達也 ONUKI, Tatsuya
  • 上妻宗広 KOZUMA, Munehiro
  • 青木健 AOKI, Takeshi
  • 岡本佑樹 OKAMOTO, Yuki
  • 池田隆之 IKEDA, Takayuki
Priority Data
2020-13167303.08.2020JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract
(EN) Provided is a semiconductor device having a novel configuration. This semiconductor device includes a digital calculator, an analog calculator, a first memory circuit, and a second memory circuit. The analog calculator, the first memory circuit, and the second memory circuit each include a transistor having an oxide semiconductor in a channel formation region. The first memory circuit has the function of supplying first weight data as digital data to the digital calculator, and the digital calculator has the function of performing a product-sum operation using the first weight data. The second memory circuit has the function of supplying second weight data as analog data to the analog calculator, and the analog calculator has the function of performing a product-sum operation using the second weight data. In at least one of the transistors that are provided respectively to the analog calculator and to the second memory circuit, and that each have an oxide semiconductor in the channel formation region thereof, a current quantity flowing in between a source and a drain is a current quantity that flows when the relevant transistor is running in a sub-threshold region.
(FR) L'invention concerne un dispositif à semi-conducteur ayant une nouvelle configuration. Le dispositif à semi-conducteur selon l'invention comprend un calculateur numérique, un calculateur analogique, un premier circuit de mémoire et un second circuit de mémoire. Le calculateur analogique, le premier circuit de mémoire et le second circuit de mémoire comprennent chacun un transistor ayant un semi-conducteur à oxyde dans une région de formation de canal. Le premier circuit de mémoire a pour fonction de fournir des premières données de poids sous forme de données numériques au calculateur numérique et le calculateur numérique a pour fonction de réaliser une opération multiplication-addition à l'aide des premières données de poids. Le second circuit de mémoire a pour fonction de fournir des secondes données de poids en tant que données analogiques au calculateur analogique et le calculateur analogique a pour fonction de réaliser une opération multiplication-addition à l'aide des secondes données de poids. Dans au moins l'un des transistors qui sont fournis respectivement au calculateur analogique et au second circuit de mémoire et qui ont chacun un semi-conducteur à oxyde dans sa région de formation de canal, une quantité de courant circulant entre une source et un drain est une quantité de courant qui circule lorsque le transistor concerné est en marche dans une région inférieure à un seuil.
(JA) 新規な構成の半導体装置を提供すること。 デジタル演算器と、アナログ演算器と、第1メモリ回路と、第2メモリ回路と、を有し、アナログ演算器、第1メモリ回路、および第2メモリ回路は、それぞれ、チャネル形成領域に酸化物半導体を有するトランジスタを含み、第1メモリ回路は、第1重みデータをデジタルデータとして、デジタル演算器に供給する機能を有し、デジタル演算器は、第1重みデータを用いて積和演算を行う機能を有し、第2メモリ回路は、第2重みデータをアナログデータとして、アナログ演算器に供給する機能を有し、アナログ演算器は、第2重みデータを用いて積和演算を行う機能を有し、アナログ演算器、および第2メモリ回路が含む、チャネル形成領域に酸化物半導体を有するトランジスタの少なくとも一において、ソース-ドレイン間に流れる電流量は、当該トランジスタがサブスレッショルド領域で動作するときに流れる電流量である、半導体装置。
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