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1. WO2022028113 - SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE

Publication Number WO/2022/028113
Publication Date 10.02.2022
International Application No. PCT/CN2021/099874
International Filing Date 11.06.2021
IPC
H01L 21/8242 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8242Dynamic random access memory structures (DRAM)
H01L 27/108 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
CPC
H01L 27/108
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
H01L 27/10805
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10805with one-transistor one-capacitor memory cells
H01L 27/10847
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
10847for structures comprising one transistor one-capacitor memory cells
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 李森 LI, Sen
  • 夏军 XIA, Jun
Agents
  • 北京名华博信知识产权代理有限公司 BOXIN CHINA INTELLECTUAL PROPERTY
Priority Data
202010779931.105.08.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE
(FR) PROCÉDÉ DE FABRICATION DE STRUCTURE SEMI-CONDUCTRICE ET STRUCTURE SEMI-CONDUCTRICE
(ZH) 半导体结构的制作方法及半导体结构
Abstract
(EN) Disclosed are a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate which comprises a complete grain region and a partial grain region; forming a stack on the substrate; forming a first mask layer having a first pattern on the stack; forming a first photoresist layer on the first mask layer; removing the first photoresist layer of the complete grain region after exposure and development of the first photoresist layer; and etching the stack using the first mask layer of the complete grain region and the first photoresist layer of the partial grain region as masks.
(FR) Procédé de fabrication de structure semi-conductrice et structure semi-conductrice. Le procédé de fabrication de structure semi-conductrice consiste à : fournir un substrat qui comprend une région de grain complète et une région de grain partielle ; former un empilement sur le substrat ; former une première couche de masque présentant un premier motif sur l'empilement ; former une première couche de résine photosensible sur la première couche de masque ; retirer la première couche de résine photosensible de la région de grain complète après exposition et développement de la première couche de résine photosensible ; et graver l'empilement à l'aide de la première couche de masque de la région de grain complète et de la première couche de résine photosensible de la région de grain partielle en tant que masques.
(ZH) 本公开公开了一种半导体结构的制作方法及半导体结构,半导体结构的制作方法包括:提供衬底,衬底包括完整晶粒区和非完整晶粒区;在衬底上形成叠层;在叠层上形成具有第一图案的第一掩膜层;在第一掩膜层上形成第一光刻胶层;对第一光刻胶层曝光,显影后去除完整晶粒区的第一光刻胶层;以完整晶粒区的第一掩膜层和非完整晶粒区的第一光刻胶层为掩膜对叠层进行刻蚀。
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