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1. WO2022027951 - DRIVE CIRCUIT

Publication Number WO/2022/027951
Publication Date 10.02.2022
International Application No. PCT/CN2021/076150
International Filing Date 09.02.2021
IPC
H03K 19/08 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
08using semiconductor devices
CPC
H03K 19/01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
01Modifications for accelerating switching
H03K 19/0175
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0175Coupling arrangements; Interface arrangements
H03K 19/017509
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0175Coupling arrangements; Interface arrangements
017509Interface arrangements
H03K 19/08
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
08using semiconductor devices
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 谷银川 GU, Yinchuan
Agents
  • 广州华进联合专利商标代理有限公司 ADVANCE CHINA IP LAW OFFICE
Priority Data
202010787892.X07.08.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) DRIVE CIRCUIT
(FR) CIRCUIT D'ATTAQUE
(ZH) 驱动电路
Abstract
(EN) An embodiment of the present invention relates to a drive circuit, comprising: a main drive module used to receive a first signal and generate a second signal according to the first signal, the driving capability of the second signal being higher than the driving capability of the first signal; and an auxiliary drive module connected to an output end of the main drive module, and used to receive the first signal and generate an auxiliary drive signal according to the first signal, the auxiliary drive signal being used to reduce rise time of the second signal.
(FR) Selon un mode de réalisation, la présente invention concerne un circuit d'attaque, comprenant : un module d'attaque principal utilisé pour recevoir un premier signal et générer un second signal en fonction du premier signal, la capacité d'attaque du second signal étant supérieure à la capacité d'attaque du premier signal ; et un module d'attaque auxiliaire connecté à une borne de sortie du module d'attaque principal, et utilisé pour recevoir le premier signal et générer un signal d'attaque auxiliaire en fonction du premier signal, le signal d'attaque auxiliaire étant utilisé pour réduire le temps de montée du second signal.
(ZH) 本申请实施例涉及一种驱动电路包括:主驱动模块,用于接收第一信号,并根据所述第一信号生成第二信号,所述第二信号的驱动能力大于所述第一信号的驱动能力;辅助驱动模块,与所述主驱动模块的输出端连接,用于接收所述第一信号,并根据所述第一信号生成辅助驱动信号,所述辅助驱动信号用于缩短所述第二信号的上升时间。
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