Processing

Please wait...

Settings

Settings

Goto Application

1. WO2022025861 - ADAPTIVE FREQUENCY CONTROL IN INTEGRATED CIRCUITS

Publication Number WO/2022/025861
Publication Date 03.02.2022
International Application No. PCT/US2020/043749
International Filing Date 27.07.2020
IPC
G06F 1/00 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
G06F 1/324 2019.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of a power-saving mode
3234Power saving characterised by the action undertaken
324by lowering clock frequency
H03K 5/13 2014.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulation of pulses not covered by one of the other main groups of this subclass
13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
H03K 5/00 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulation of pulses not covered by one of the other main groups of this subclass
CPC
G06F 1/04
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
08Clock generators with changeable or programmable clock frequency
G06F 1/324
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
324by lowering clock frequency
H03K 5/00006
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulating of pulses not covered by one of the other main groups of this subclass
00006Changing the frequency
H03K 5/13
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulating of pulses not covered by one of the other main groups of this subclass
13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
Applicants
  • GOOGLE LLC [US]/[US]
Inventors
  • BASEHORE, Derek
  • SANDERS, Nick
Agents
  • COLBY, Michael, K.
Priority Data
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) ADAPTIVE FREQUENCY CONTROL IN INTEGRATED CIRCUITS
(FR) COMMANDE DE FRÉQUENCE ADAPTATIVE DANS DES CIRCUITS INTÉGRÉS
Abstract
(EN) This document describes systems and techniques for adaptive frequency control in integrated circuits (202). In response to operating conditions that permit a lower frequency (322) of a clock signal (306), the described systems and techniques dynamically reduce the clock frequency (322) without adjusting the frequency (318) of an input clock signal (302). The clock frequency (322) is decreased by gating a fraction of the input clock signal (302) and stretching the ungated cycles by an offset amount. By dynamically adjusting the clock frequency (322) in this manner, an integrated circuit (202) can change its clock frequency (322) more quickly and maintain the supply voltage closer to a lower voltage limit to reduce power consumption and allow safer operations.
(FR) L'invention concerne des systèmes et des techniques pour la commande de fréquence adaptative dans des circuits intégrés (202). En réponse à des conditions de fonctionnement qui permettent une fréquence inférieure (322) d'un signal d'horloge (306), les systèmes et les techniques décrits réduisent dynamiquement la fréquence d'horloge (322) sans ajuster la fréquence (318) d'un signal d'horloge d'entrée (302). La fréquence d'horloge (322) est diminuée par le blocage d'une fraction du signal d'horloge d'entrée (302) et l'étirement des cycles non bloqués selon une quantité de décalage. En réglant dynamiquement la fréquence d'horloge (322) de cette manière, un circuit intégré (202) peut modifier sa fréquence d'horloge (322) plus rapidement et maintenir la tension d'alimentation plus proche d'une limite de tension inférieure pour réduire la consommation d'énergie et permettre des opérations plus sûres.
Latest bibliographic data on file with the International Bureau