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1. WO2022011192 - AUTOMATED ASSISTED CIRCUIT VALIDATION

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Publication Number WO/2022/011192
Publication Date 13.01.2022
International Application No. PCT/US2021/040965
International Filing Date 08.07.2021
IPC
G01R 31/3183 2006.1
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
3183Generation of test inputs, e.g. test vectors, patterns or sequences
G01R 31/3185 2006.1
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
3185Reconfiguring for testing, e.g. LSSD, partitioning
CPC
G01R 31/31835
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
3183Generation of test inputs, e.g. test vectors, patterns or sequences
318342by preliminary fault modelling, e.g. analysis, simulation
31835Analysis of test coverage or failure detectability
G01R 31/318357
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
3183Generation of test inputs, e.g. test vectors, patterns or sequences
318342by preliminary fault modelling, e.g. analysis, simulation
318357Simulation
G06F 2119/02
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2119Details relating to the type or aim of the analysis or the optimisation
02Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
G06F 30/323
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
32Circuit design at the digital level
323Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
G06F 30/3308
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
32Circuit design at the digital level
33Design verification, e.g. functional simulation or model checking
3308using simulation
G06F 30/333
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
32Circuit design at the digital level
333Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
Applicants
  • TEKTRONIX, INC. [US]/[US]
Inventors
  • BURGESS, David Everett
Agents
  • HARRINGTON, Andrew, J.
Priority Data
17/370,97608.07.2021US
63/050,05309.07.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) AUTOMATED ASSISTED CIRCUIT VALIDATION
(FR) VALIDATION DE CIRCUIT ASSISTÉ AUTOMATISÉE
front page image
Abstract
(EN) A method comprising categorizing nodes of a fabricated circuit as being priority nodes and nodes as being inferior nodes; evaluating a first priority node by automatically designating for verification the first priority node, and ascertaining whether a measured signal from the first priority node meets a pass-fail criterion for the first priority node; evaluating, when the measured signal from the first priority node meets the pass-fail criterion, a second priority node by automatically designating for verification the second priority node, and ascertaining whether a measured signal from the second priority node meets a pass-fail criterion for the second priority node; and evaluating, when the measured signal from the first priority node does not meet the pass-fail criterion, a first inferior node, by automatically designating for verification the first inferior node, and ascertaining whether a measured signal from the first inferior node meets a pass-fail criterion for the first inferior node.
(FR) Procédé consistant à catégoriser des nœuds d'un circuit fabriqué comme étant des nœuds prioritaires et des nœuds comme étant des nœuds inférieurs ; à évaluer un premier nœud prioritaire en désignant automatiquement pour une vérification le premier nœud prioritaire, et à déterminer si un signal mesuré provenant du premier nœud prioritaire satisfait un critère de réussite/d'échec pour le premier nœud prioritaire ; à évaluer, lorsque le signal mesuré provenant du premier nœud prioritaire satisfait le critère de réussite/d'échec, un second nœud prioritaire en désignant automatiquement pour une vérification le second nœud prioritaire, et à déterminer si un signal mesuré provenant du second nœud prioritaire satisfait un critère de réussite/d'échec pour le second nœud prioritaire ; et à évaluer, lorsque le signal mesuré provenant du premier nœud prioritaire ne satisfait pas le critère de réussite/d'échec, un premier nœud inférieur, en désignant automatiquement pour une vérification le premier nœud inférieur, et en déterminant si un signal mesuré provenant du premier nœud inférieur satisfait un critère de réussite/d'échec pour le premier nœud inférieur.
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