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1. WO2022010546 - METHOD OF FORMING SPLIT GATE MEMORY CELLS WITH THINNER TUNNEL OXIDE

Publication Number WO/2022/010546
Publication Date 13.01.2022
International Application No. PCT/US2021/019297
International Filing Date 23.02.2021
IPC
H01L 27/11521 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11521characterised by the memory core region
H01L 29/423 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
H01L 21/28 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
Applicants
  • SILICON STORAGE TECHNOLOGY, INC. [US]/[US]
Inventors
  • YANG, Jeng-Wei
  • WU, Man Tang
  • FAN, Boolean
  • DO, Nhan
Agents
  • LIMBACH, Alan
Priority Data
17/179,05718.02.2021US
63/049,77509.07.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) METHOD OF FORMING SPLIT GATE MEMORY CELLS WITH THINNER TUNNEL OXIDE
(FR) PROCÉDÉ DE FORMATION DE CELLULES DE MÉMOIRE À GRILLES DIVISÉES AVEC OXYDE AMINCI DE TUNNEL
Abstract
(EN) A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.
(FR) Un procédé de formation d'une cellule de mémoire consiste à former un premier bloc de polysilicium sur une surface supérieure d'un substrat semi-conducteur et dont une surface supérieure et une surface latérale se coupent au niveau d'un bord tranchant ; à former une couche d'oxyde avec une première partie sur la surface supérieure, avec une deuxième partie directement sur la surface latérale et avec une troisième partie directement sur le bord tranchant ; à réaliser une gravure amincissant la couche d'oxyde de manière non uniforme pour que la troisième partie soit plus mince que les première et deuxième parties ; à réaliser un dépôt d'oxyde épaississant les première, deuxième et troisième parties de la couche d'oxyde, pour qu'après le dépôt d'oxyde, la troisième partie soit plus mince que les première et seconde parties ; et à former un second bloc de polysilicium dont une partie repose directement sur la première partie de la couche d'oxyde et une autre partie directement sur la troisième partie de la couche d'oxyde.
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