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1. WO2022010016 - METHOD AND DEVICE FOR PROCESSING READ-WRITE-OPERATION INSTRUCTION OF PROCESSING-IN-MEMORY

Publication Number WO/2022/010016
Publication Date 13.01.2022
International Application No. PCT/KR2020/009164
International Filing Date 13.07.2020
IPC
G06F 9/30 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 15/78 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
G11C 7/10 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G06F 15/78
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
G06F 15/7821
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
7821Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
G06F 9/30
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/3004
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
3004to perform operations on memory
G11C 7/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/1006
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Applicants
  • 전자부품연구원 KOREA ELECTRONICS TECHNOLOGY INSTITUTE [KR]/[KR]
Inventors
  • 김병수 KIM, Byung Soo
  • 장영종 JANG, Young Jong
  • 김영규 KIM, Young Kyu
Agents
  • 특허법인 지명 JIMYUNG PATENT FIRM
Priority Data
10-2020-008557410.07.2020KR
Publication Language Korean (ko)
Filing Language Korean (KO)
Designated States
Title
(EN) METHOD AND DEVICE FOR PROCESSING READ-WRITE-OPERATION INSTRUCTION OF PROCESSING-IN-MEMORY
(FR) PROCÉDÉ ET DISPOSITIF PERMETTANT DE TRAITER UNE INSTRUCTION D'OPÉRATION DE LECTURE-D'ÉCRITURE D'UN TRAITEMENT EN MÉMOIRE
(KO) 프로세싱인메모리의 읽고-쓰기-연산 명령어 처리 방법 및 장치
Abstract
(EN) The present invention proposes a processing-in-memory (PIM) internal device and a method for including a read-write-operation instruction corresponding to a new instruction in an instruction set and processing the read-write-operation instruction, so as to maximize performance of PIM. The present invention provides the following solutions comprising: an instruction set of PIM, the instruction set including a read-write-operation instruction in addition to read, write, read-operation, and write-operation instructions, wherein the read-write-operation instruction simultaneously performs reading and writing for a PIM operation result by writing in a target address simultaneously while returning the PIM operation result to a computer system; and an instruction processor in the PIM, the instruction processor including a response data selector and a finite state machine in order to process the read-write-operation instruction, wherein the response data selector of the instruction processor includes a selector for selecting one of a response data signal and an operation result, and a three-state buffer for opening or closing response data, and the finite state machine of the instruction processor outputs a response acceptance signal and a response selection signal for controlling the three-state buffer and the selector of the response data selector.
(FR) La présente invention porte sur un dispositif interne de traitement en mémoire (PIM) et sur un procédé permettant d'inclure une instruction d'opération de lecture-d'écriture correspondant à une nouvelle instruction dans un jeu d'instructions et de traiter l'instruction l'opération de lecture-d'écriture de sorte à maximiser les performances du traitement PIM. La présente invention concerne les solutions suivantes comprenant : un jeu d'instructions de traitement PIM, le jeu d'instructions comprenant une instruction d'opération de lecture-d'écriture en plus d'instructions de lecture, d'écriture, d'opération de lecture et d'opération d'écriture, l'instruction d'opération de lecture-d'écriture effectuant simultanément une lecture et une écriture pour un résultat d'opération de traitement PIM par écriture dans une adresse cible en renvoyant en même temps le résultat d'opération traitement PIM à un système informatique ; et un processeur d'instructions dans le traitement PIM, le processeur d'instructions comprenant un sélecteur de données de réponse et une machine à états finis afin de traiter l'instruction d'opération de lecture-d'écriture, le sélecteur de données de réponse du processeur d'instruction comprenant un sélecteur pour sélectionner soit un signal de données de réponse, soit un résultat d'opération, et un tampon à trois états pour ouvrir ou fermer des données de réponse, et la machine à états finis du processeur d'instructions émettant un signal d'acceptation de réponse et un signal de sélection de réponse pour commander le tampon à trois états et le sélecteur du sélecteur de données de réponse.
(KO) 본발명은 PIM의 성능을 극대화하기 위하여 새로운 명령어인 읽고-쓰기-연산 명령어(READ-WRITE-OPERATION instruction)를 명령어세트에 포함시키고 이 읽고-쓰기-연산 명령어를 처리하기 위한 방법 및 PIM 내부 장치를 제안한다. 본발명은 다음과 같은 과제 해결 수단을 제공한다. - 프로세싱인메모리(PIM)의 명령어세트에 읽기, 쓰기, 읽기-연산, 쓰기-연산 명령어 이외에 읽고-쓰기-연산(READ-WRITE-OPERATION) 명령어를 포함시킴, - 읽고-쓰기-연산 명령어는 PIM의 연산 결과를 컴퓨터 시스템에 돌려줌과 동시에 목적 주소에 쓰기를 하여, PIM의 연산 결과에 대한 읽기 및 쓰기를 동시에 수행, - 읽고-쓰기-연산 명령어를 처리하기 위하여 유한상태기계 및 응답 데이터 선택기를 포함하는, PIM 내부의 명령어 처리기, - 상기 명령어 처리기의 응답 데이터 선택기는, 응답 데이터 신호와 연산 결과 중 하나를 선택하는 선택기와, 응답 데이터를 열거나 막는 3상 버퍼를 포함, - 상기 명령어 처리기의 유한상태기계는 상기 응답 데이터 선택기의 선택기와 3상 버퍼를 제어하는 응답 선택 신호와 응답 허락 신호를 출력.
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