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1. WO2022010015 - MEMORY MANAGEMENT METHOD AND APPARATUS FOR PROCESSING IN MEMORY

Publication Number WO/2022/010015
Publication Date 13.01.2022
International Application No. PCT/KR2020/009163
International Filing Date 13.07.2020
IPC
G06F 13/16 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 3/06 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from, or digital output to, record carriers
G06F 15/78 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
Applicants
  • 전자부품연구원 KOREA ELECTRONICS TECHNOLOGY INSTITUTE [KR]/[KR]
Inventors
  • 김병수 KIM, Byung Soo
  • 장영종 JANG, Young Jong
  • 김영규 KIM, Young Kyu
Agents
  • 특허법인 지명 JIMYUNG PATENT FIRM
Priority Data
10-2020-008557310.07.2020KR
Publication Language Korean (ko)
Filing Language Korean (KO)
Designated States
Title
(EN) MEMORY MANAGEMENT METHOD AND APPARATUS FOR PROCESSING IN MEMORY
(FR) PROCÉDÉ DE GESTION DE MÉMOIRE ET APPAREIL DE TRAITEMENT EN MÉMOIRE
(KO) 프로세싱인메모리의 메모리 관리 방법 및 장치
Abstract
(EN) The present invention relates to a memory management method for maximizing the performance of processing in memory (PIM), and the objective of the present invention is to improve the performance of PIM by reducing unnecessary DRAM access time of PIM. To this end, when an instruction processing device processes a PIM instruction packet, a destination address access request having a high possibility that read and write operations of an internal memory are continuously performed is processed with low priority. By requesting a destination address with a low priority, a row address of an open page in the internal memory can be matched with a row address to which a PIM instruction packet processing result is returned. In addition, the instruction processing device in PIM maintains memory write and read addresses that have been previously requested. A previous memory address maintained by the instruction processing device is compared to the address of a packet to be processed, and a memory controller is informed in advance of the comparison result through a page close signal. According to the present invention, an open page hit rate of an internal memory is improved, and a loss in performance due to a page miss, which occurs when internal memory management is performed in an open page mode, is reduced.
(FR) La présente invention se rapporte à un procédé de gestion de mémoire permettant de maximiser les performances de traitement en mémoire (PIM), et l'objectif de la présente invention est d'améliorer les performances d'un traitement PIM en réduisant le temps d'accès à une mémoire DRAM inutile du traitement PIM. À cet effet, lorsqu'un dispositif de traitement d'instructions traite un paquet d'instructions de traitement PIM, une demande d'accès à une adresse de destination ayant une possibilité élevée que des opérations de lecture et d'écriture d'une mémoire interne sont effectuées en continu est traitée avec une faible priorité. En demandant une adresse de destination ayant une faible priorité, une adresse de rangée d'une page ouverte dans la mémoire interne peut être mise en correspondance avec une adresse de rangée à laquelle un résultat de traitement de paquet d'instructions de traitement PIM est renvoyé. De plus, le dispositif de traitement d'instructions dans un traitement PIM maintient des adresses d'écriture et de lecture de mémoire qui ont été précédemment demandées. Une précédente adresse de mémoire conservée par le dispositif de traitement d'instructions est comparée à l'adresse d'un paquet à traiter, et un dispositif de commande de mémoire est informé à l'avance du résultat de comparaison au moyen d'un signal de fermeture de page. Selon la présente invention, un taux de réussite de page ouverte d'une mémoire interne est amélioré, et une perte de performance due à un manque de page, qui se produit lorsqu'une gestion de mémoire interne est réalisée dans un mode de page ouverte, est réduite.
(KO) 본발명은 PIM의 성능을 극대화하기 위한 메모리 관리 방법으로서 프로세싱인메모리(PIM)의 불필요한 DRAM 접근 시간을 줄임으로써 PIM의 성능을 향상시키는 것을 목적으로 한다. 이를 위해 명령어 처리장치가 PIM 명령어패킷을 처리할 때, 내부 메모리의 읽기와 쓰기 동작이 연이어 진행될 가능성이 높은 목적주소 접근 요청을 후순위로 처리한다. 목적주소를 후순위로 요청함에 의해, 내부 메모리의 오픈 되어 있는 페이지의 행-주소와 PIM 명령어패킷 처리 결과를 돌려줄 행 주소가 일치될 수 있다. 또한 PIM 내부의 명령어 처리장치는 이전에 요청했던 메모리 쓰기 및 읽기 주소를 유지한다. 명령어 처리장치가 유지하고 있는 이전 메모리 주소와, 처리해야 할 패킷의 주소를 비교하고 비교 결과를 페이지 닫음 신호를 통해 메모리 제어기에게 미리 알려준다. 본 발명에 의해, 내부 메모리의 오픈페이지 적중률(open page hit rate)이 향상되고, 내부 메모리 관리가 오픈페이지 모드로 운영될 때 발생하는 페이지 불일치(page miss)로 인한 성능 손실이 줄어든다.
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