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1. WO2022009823 - THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY, AND THIN FILM TRANSISTOR PRODUCTION METHOD

Publication Number WO/2022/009823
Publication Date 13.01.2022
International Application No. PCT/JP2021/025258
International Filing Date 05.07.2021
IPC
H01L 29/786 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
H01L 21/316 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
314Inorganic layers
316composed of oxides or glassy oxides or oxide-based glass
H01L 21/318 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
314Inorganic layers
318composed of nitrides
H01L 21/336 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
H01L 21/363 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
36Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
363using physical deposition, e.g. vacuum deposition, sputtering
CPC
H01L 21/02107
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02107Forming insulating materials on a substrate
H01L 21/31
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
H01L 29/66477
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
H01L 29/786
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
786Thin film transistors, ; i.e. transistors with a channel being at least partly a thin film
Applicants
  • 凸版印刷株式会社 TOPPAN INC. [JP]/[JP]
Inventors
  • 池田 典昭 IKEDA, Noriaki
Agents
  • 特許業務法人第一国際特許事務所 PATENT CORPORATE BODY DAI-ICHI KOKUSAI TOKKYO JIMUSHO
Priority Data
2020-11680407.07.2020JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY, AND THIN FILM TRANSISTOR PRODUCTION METHOD
(FR) TRANSISTOR À COUCHES MINCES, RÉSEAU DE TRANSISTORS À COUCHES MINCES ET PROCÉDÉ DE PRODUCTION DE TRANSISTORS À COUCHES MINCES
(JA) 薄膜トランジスタ、薄膜トランジスタアレイおよび薄膜トランジスタの製造方法
Abstract
(EN) The purpose of the present invention is to provide a thin film transistor that has preferable element characteristics and high flexibility, a thin film transistor array, and a thin film transistor production method. Thus, the thin film transistor of the present invention has an insulative substrate, a gate electrode, a first gate insulating layer, a second gate insulating layer, a semiconductor layer, an insulative protection layer, a source electrode, and a drain electrode. The first gate insulating layer comprises an insulating material including an organic material, the second gate insulating layer comprises an inorganic insulating material, the thickness of the second gate insulating layer is thinner than the thickness of the first gate insulating layer, and the second gate insulating layer is formed only in a range overlapping the semiconductor layer or the protection layer.
(FR) L'objet de la présente invention est de fournir un transistor à couches minces qui a des caractéristiques d'élément préférables et une flexibilité élevée, un réseau de transistors à couches minces, et un procédé de production de transistor à couches minces. Ainsi, le transistor à couches minces de la présente invention comporte un substrat isolant, une électrode de grille, une première couche d'isolation de grille, une seconde couche d'isolation de grille, une couche semi-conductrice, une couche de protection isolante, une électrode de source et une électrode de drain. La première couche d'isolation de grille comprend un matériau isolant comprenant un matériau organique, la seconde couche d'isolation de grille comprend un matériau isolant inorganique, l'épaisseur de la seconde couche d'isolation de grille est inférieure à l'épaisseur de la première couche d'isolation de grille, et la seconde couche d'isolation de grille est formée uniquement dans une plage chevauchant la couche semi-conductrice ou la couche de protection.
(JA) 本発明は、良好な素子特性を有し、かつ高い可撓性を有する薄膜トランジスタ、薄膜トランジスタアレイおよび薄膜トランジスタの製造方法を提供することを目的とする。このため、本発明の薄膜トランジスタは、絶縁性の基板と、ゲート電極と、第1のゲート絶縁層と、第2のゲート絶縁層と、半導体層と、絶縁性の保護層と、ソース電極およびドレイン電極とを有し、第1のゲート絶縁層は、有機材料を含む絶縁材料からなり、第2のゲート絶縁層は、無機絶縁材料からなり、第2のゲート絶縁層の膜厚は、第1のゲート絶縁層の膜厚より薄く、第2のゲート絶縁層は、半導体層または保護層と重畳する範囲にのみ形成されている。
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