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1. WO2022009741 - ELECTRONIC CONTROL DEVICE

Publication Number WO/2022/009741
Publication Date 13.01.2022
International Application No. PCT/JP2021/024626
International Filing Date 29.06.2021
IPC
G06F 9/52 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
G06F 9/54 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
54Interprogram communication
G06F 12/02 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
G06F 15/167 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
163Interprocessor communication
167using a common memory, e.g. mailbox
CPC
G06F 12/02
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
G06F 15/167
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
163Interprocessor communication
167using a common memory, e.g. mailbox
G06F 9/52
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
G06F 9/54
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
54Interprogram communication
Applicants
  • 日立Astemo株式会社 HITACHI ASTEMO, LTD. [JP]/[JP]
Inventors
  • 堀口 辰也 HORIGUCHI Tatsuya
  • 石郷岡 祐 ISHIGOOKA Tasuku
  • 大塚 敏史 OTSUKA Satoshi
  • 芹沢 一 SERIZAWA Kazuyoshi
  • 村上 隆 MURAKAMI Takashi
Agents
  • 特許業務法人開知国際特許事務所 KAICHI IP
Priority Data
2020-11716107.07.2020JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) ELECTRONIC CONTROL DEVICE
(FR) DISPOSITIF DE COMMANDE ÉLECTRONIQUE
(JA) 電子制御装置
Abstract
(EN) Provided is an electronic control device with which it is possible to raise the efficiency of data delivery between applications in time-synchronized design. This electronic control device comprises: a processor including a plurality of cores operating on different cycles, said cores executing a plurality of processes; and a memory including a plurality of memory areas that can be individually accessed for each of the plurality of cores that execute a plurality of processes. The electronic control device changes, in accordance with the progress of the processes, the memory areas accessible by a preceding process that performs data writing and a subsequent process that performs data reading. The processor searches for a writable memory area into which the latest result of processing has not been written yet and which is not in the middle of a read, reserves a new memory area when no writable memory areas exist, and sets the new memory area as the destination to which the result of processing is written, whereby the result of processing is delivered from the preceding process to the subsequent process.
(FR) L'invention concerne un dispositif de commande électronique avec lequel il est possible d'augmenter l'efficacité de distribution de données entre des applications dans une conception à synchronisation temporelle. Ce dispositif de commande électronique comprend : un processeur comprenant une pluralité de cœurs fonctionnant sur différents cycles, lesdits cœurs exécutant une pluralité de processus ; et une mémoire comprenant une pluralité de zones de mémoire auxquelles peut accéder individuellement chaque cœur de la pluralité de cœurs qui exécutent une pluralité de processus. Le dispositif de commande électronique change, selon la progression des processus, les zones de mémoire accessibles par un processus précédent qui effectue une écriture de données et un processus suivant qui effectue une lecture de données. Le processeur recherche une zone de mémoire inscriptible dans laquelle le résultat de traitement le plus récent n'a pas encore été écrit et qui n'est pas en cours de lecture, réserve une nouvelle zone de mémoire lorsqu'aucune zone de mémoire inscriptible n'existe, et définit la nouvelle zone de mémoire en tant que destination sur laquelle le résultat de traitement est écrit, ce par quoi le résultat du traitement est fourni du processus précédent au processus suivant.
(JA) 時刻同期型設計におけるアプリケーション間におけるデータ受渡の効率を高めることが可能な電子制御装置が提供される。電子制御装置は、異なる周期で動作する複数の処理を実行する複数のコアを含むプロセッサと、複数の処理を実行する前記複数のコアごとにそれぞれアクセス可能な複数のメモリ領域を含むメモリと、を備え、データ書込みを行う先行処理とデータ読出しを行う後続処理とがそれぞれアクセス可能な前記メモリ領域を処理の進捗に応じて変更する。プロセッサは、最新の処理の結果が書き込まれておらず、かつ読出し中でない書込み可能なメモリ領域を探索し、書込み可能なメモリ領域が存在しない場合、新たなメモリ領域を確保し、新たなメモリ領域を処理の結果の書き込み先とすることで、先行処理から後続処理へ処理の結果を受け渡す。
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