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1. WO2022009705 - SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE

Publication Number WO/2022/009705
Publication Date 13.01.2022
International Application No. PCT/JP2021/024161
International Filing Date 25.06.2021
IPC
H01L 23/12 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
CPC
H01L 2224/0603
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
0601Structure
0603Bonding areas having different sizes, e.g. different heights or widths
H01L 2224/18
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
18High density interconnect [HDI] connectors; Manufacturing methods related thereto
H01L 23/12
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
Applicants
  • 株式会社デンソー DENSO CORPORATION [JP]/[JP]
Inventors
  • 大澤 青吾 OOSAWA Seigo
  • 犬塚 仁浩 INUTSUKA Yoshihiro
  • 中野 貴博 NAKANO Takahiro
  • 大倉 康嗣 OOKURA Yasushi
Agents
  • 特許業務法人ゆうあい特許事務所 YOU-I PATENT FIRM
Priority Data
2020-11942310.07.2020JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET MODULE À SEMI-CONDUCTEUR
(JA) 半導体装置および半導体モジュール
Abstract
(EN) Provided is a semiconductor device having a fan out package structure and comprising a semiconductor element (11) that has a first electrode pad (111) and a second electrode pad (112) on a surface (11a), a sealing member (12) that is composed of an insulating resin material and covers a side surface (11c) that connects the surface and a rear surface (11b) of the semiconductor element, and a rewiring layer (13) that covers the surface of the semiconductor element and a portion of the sealing member. The rewiring layer includes an insulating layer (131) composed of an insulating resin material, a first rewire (132) at least a portion of which is arranged on the boundary between the side surface of the semiconductor element and the sealing member, and a second rewire (133) which is electrically connected to the second electrode pad, and is electrically independent from the first rewire, at least a portion of the second rewire being extended outward of the outline of the semiconductor element across the first rewire.
(FR) L'invention concerne un dispositif à semi-conducteur ayant une structure de boîtier de sortance et comprenant un élément semi-conducteur (11) qui présente une première pastille d'électrode (111) et une seconde pastille d'électrode (112) sur une surface (11a), un élément d'étanchéité (12) qui est composé d'un matériau de résine isolant et qui recouvre une surface latérale (11c) reliant la surface (11a) à une surface arrière (11b) de l'élément semi-conducteur, et une couche de recâblage (13) qui recouvre la surface de l'élément semi-conducteur et une partie de l'élément d'étanchéité. La couche de recâblage comprend une couche isolante (131) composée d'un matériau de résine isolant, d'un premier recâblage (132) dont au moins une partie est disposée sur la limite entre la surface latérale de l'élément semi-conducteur et l'élément d'étanchéité, et un second recâblage (133) qui est électriquement connecté à la seconde pastille d'électrode, et est électriquement indépendant du premier recâblage, au moins une partie du second recâblage étant étendue vers l'extérieur du contour de l'élément semi-conducteur à travers le premier recâblage.
(JA) ファンアウトパッケージ構造の半導体装置であって、表面(11a)に第1電極パッド(111)と第2電極パッド(112)とを有する半導体素子(11)と、絶縁性の樹脂材料で構成され、半導体素子のうち前記表面と裏面(11b)とを繋ぐ側面(11c)を覆う封止材(12)と、半導体素子の表面および封止材の一部を覆う再配線層(13)と、を備える。再配線層は、絶縁性の樹脂材料で構成された絶縁層(131)と、少なくとも一部が半導体素子の側面と封止材との境界の上に配置される第1再配線(132)と、第2電極パッドに電気的に接続されると共に、少なくとも一部が第1再配線を跨いで半導体素子の外郭の外側まで延設され、第1再配線とは電気的に独立している第2再配線(133)と、を有してなる。
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