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1. WO2022007521 - PREPARATION METHOD FOR SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE

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Publication Number WO/2022/007521
Publication Date 13.01.2022
International Application No. PCT/CN2021/095570
International Filing Date 24.05.2021
IPC
H01L 21/28 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
CPC
H01L 21/28
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
H01L 21/28008
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
28008Making conductor-insulator-semiconductor electrodes
H01L 21/28247
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
28008Making conductor-insulator-semiconductor electrodes
28017the insulator being formed after the semiconductor body, the semiconductor being silicon
28247passivation or protection of the electrode, e.g. using re-oxidation
H01L 29/49
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
H01L 29/4925
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
4916the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
4925with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 吴公一 WU, Gongyi
  • 于有权 YU, Youquan
  • 陆勇 LU, Yong
Agents
  • 北京派特恩知识产权代理有限公司 CHINA PAT INTELLECTUAL PROPERTY OFFICE
Priority Data
202010663904.810.07.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) PREPARATION METHOD FOR SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE
(FR) PROCÉDÉ DE PRÉPARATION POUR UNE STRUCTURE SEMI-CONDUCTRICE ET STRUCTURE SEMI-CONDUCTRICE
(ZH) 一种半导体结构的制备方法及半导体结构
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Abstract
(EN) The present application provides a preparation method for a semiconductor structure and the semiconductor structure. The preparation method for the semiconductor structure comprises the following steps: sequentially forming a first conductive layer, a second conductive layer and a passivation layer on a semiconductor substrate; patterning the passivation layer and the second conductive layer to form a primary gate pattern, leaving an area of the first conductive layer not covered by the primary gate pattern exposed; performing plasma processing on the primary gate pattern to form a first protective layer on the side wall of the second conductive layer; forming a dielectric layer on the side wall of the primary gate pattern and the side surface of the first protective layer; removing the exposed area of the first conductive layer, and reserving the area of the first conductive layer covered by the primary gate pattern; and forming a second protective layer on the exposed side wall of the first conductive layer, wherein the second protective layer and the dielectric layer are used as an isolation layer of a gate structure.
(FR) La présente invention concerne un procédé de préparation pour une structure semi-conductrice et la structure semi-conductrice. Le procédé de préparation pour la structure semi-conductrice comprend les étapes suivantes consistant à : former séquentiellement une première couche conductrice, une seconde couche conductrice et une couche de passivation sur un substrat semi-conducteur ; former des motifs sur la couche de passivation et la seconde couche conductrice pour former un motif de porte primaire, laissant une zone de la première couche conductrice non recouverte par le motif de porte primaire exposé ; exécuter un traitement par plasma sur le motif de porte primaire pour former une première couche de protection sur la paroi latérale de la seconde couche conductrice ; former une couche diélectrique sur la paroi latérale du motif de porte primaire et la surface latérale de la première couche de protection ; éliminer la zone exposée de la première couche conductrice, et réserver la zone de la première couche conductrice recouverte par le motif de porte primaire ; et former une seconde couche de protection sur la paroi latérale exposée de la première couche conductrice, la seconde couche de protection et la couche diélectrique étant utilisées en tant que couche d'isolation d'une structure de porte.
(ZH) 本申请提供一种半导体结构的制备方法及半导体结构。所述半导体结构的制备方法，包括如下步骤：在半导体衬底上依次形成第一导电层、第二导电层及钝化层；图形化所述钝化层及第二导电层，形成初级栅极图案，所述第一导电层未被所述初级栅极图案遮挡的区域暴露；对所述初级栅极图案进行等离子体处理，以在所述第二导电层的侧壁形成第一保护层；在所述初级栅极图案侧壁及第一保护层侧面形成介质层；去除暴露的第一导电层，保留被所述初级栅极图案覆盖的第一导电层；在所述第一导电层暴露的侧壁形成第二保护层，所述第二保护层及所述介质层作为所述栅极结构的隔离层。
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