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1. WO2022006775 - METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES WITH CHANNEL STRUCTURES HAVING PLUM BLOSSOM SHAPE

Publication Number WO/2022/006775
Publication Date 13.01.2022
International Application No. PCT/CN2020/100868
International Filing Date 08.07.2020
IPC
H01L 27/1157 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11568characterised by the memory core region
1157with cell select transistors, e.g. NAND
H01L 27/11582 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
1158with source and drain on different levels, e.g. with sloping channels
11582the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11556 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11551characterised by three-dimensional arrangements, e.g. with cells on different height levels
11553with source and drain on different levels, e.g. with sloping channels
11556the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11551 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11551characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/11524 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11521characterised by the memory core region
11524with cell select transistors, e.g. NAND
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • GENG, Wanbo
  • XUE, Lei
  • LIU, Xiaoxin
  • GAO, Tingting
  • CHENG, Weihua
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES WITH CHANNEL STRUCTURES HAVING PLUM BLOSSOM SHAPE
(FR) PROCÉDÉS DE FORMATION DE DISPOSITIFS MÉMOIRES TRIDIMENSIONNELS À STRUCTURES DE TYPE CANAL PRÉSENTANT LA FORME D'UNE FLEUR DE PRUNIER
Abstract
(EN) Three-dimensional (3D) memory devices and methods for forming the same are disclosed. A channel hole extending vertically above a substrate and having a plum blossom shape in a plan view is formed. A continuous blocking layer (602), a continuous charge trapping layer (604), and a continuous tunneling layer (606) each following the plum blossom shape are formed from outside to inside in this order along sidewalls of the channel hole. A plurality of separate semiconductor channels (608A, 608B, 608C) each disposed over part of the continuous tunneling layer (606) at a respective apex of the plum blossom shape are formed.
(FR) La présente invention concerne des dispositifs mémoires tridimensionnels (3D) et leurs procédés de formation. Un trou de canal s'étendant verticalement au-dessus d'un substrat et présentant la forme d'une fleur de prunier dans une vue en plan est formé. Une couche d'arrêt continue (602), une couche de piégeage de charge continue (604) et une couche à effet tunnel continue (606), chacune respectant la forme de fleur de prunier, sont formées de l'extérieur vers l'intérieur dans cet ordre le long de parois latérales du trou de canal. Une pluralité de canaux semi-conducteurs séparés (608A, 608B, 608C), disposés chacun sur une partie de la couche à effet tunnel continue (606) au niveau d'un sommet respectif de la forme de fleur de prunier, est formée.
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