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1. WO2022006396 - METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING SUPERLATTICES WITH DIFFERENT NON-SEMICONDUCTOR THERMAL STABILITIES

Publication Number WO/2022/006396
Publication Date 06.01.2022
International Application No. PCT/US2021/040088
International Filing Date 01.07.2021
IPC
H01L 29/15 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
12characterised by the materials of which they are formed
15Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H01L 21/02 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
Applicants
  • ATOMERA INCORPORATED [US]/[US]
Inventors
  • WEEKS, Keith Doran
  • CODY, Nyles Wynn
  • HYTHA, Marek
  • MEARS, Robert J.
Agents
  • REGAN, Christopher F.
  • WOODSON, II, John F.
  • TAYLOR, Michael W.
  • WARTHER, Richard K.
  • ABID, Jack G.
  • CARUS, David S.
  • MCKINNEY, Matthew G.
Priority Data
63/047,36502.07.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING SUPERLATTICES WITH DIFFERENT NON-SEMICONDUCTOR THERMAL STABILITIES
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEUR AU MOYEN DE SUPER-RÉSEAUX AYANT DES STABILITÉS THERMIQUES NON SEMI-CONDUCTRICES DIFFÉRENTES
Abstract
(EN) A method for making a semiconductor device may include forming first and second superlattices adjacent a semiconductor layer. Each of the first and second superlattices may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The second superlattice may have a greater thermal stability with respect to non-semiconductor atoms therein than the first superlattice. The method may further include heating the first and second superlattices to cause non-semiconductor atoms from the first superlattice to migrate toward the at least one non-semiconductor monolayer of the second superlattice.
(FR) L'invention concerne un procédé de fabrication d'un dispositif à semi-conducteur pouvant consister à former des premier et second super-réseaux adjacents à une couche semi-conductrice. Les premier et second super-réseaux peuvent comprendre individuellement des groupes empilés de couches, chaque groupe de couches comprenant des monocouches semi-conductrices de base empilées délimitant une portion semi-conductrice de base, et au moins une monocouche non semi-conductrice contrainte à l’intérieur d’un réseau cristallin de parties semi-conductrices de base adjacentes. Le second super-réseau peut avoir une stabilité thermique par rapport à des atomes non semi-conducteurs en son sein plus élevée que le premier super-réseau. Le procédé peut en outre consister à chauffer les premier et second super-réseaux pour amener des atomes non semi-conducteurs du premier super-réseau à migrer vers ladite monocouche non semi-conductrice du second super-réseau.
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