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1. WO2022005905 - CALIBRATION OF SAMPLING-BASED MULTIPLYING DELAY-LOCKED LOOP (MDLL)

Publication Number WO/2022/005905
Publication Date 06.01.2022
International Application No. PCT/US2021/039181
International Filing Date 25.06.2021
IPC
H03L 7/091 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
085concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
091the phase or frequency detector using a sampling device
H03L 7/087 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
085concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
087using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/16 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
H03L 7/081 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
081provided with an additional controlled phase shifter
H03L 7/089 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
085concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
089the phase or frequency detector generating up-down pulses
H03L 7/093 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
085concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
093using special filtering or amplification characteristics in the loop
Applicants
  • QUALCOMM INCORPORATED [US]/[US]
Inventors
  • MOSLEHI BAJESTAN, Masoud
  • ZANUSO, Marco
  • HOSSAIN, Razak
  • LAKDAWALA, Hasnain
Agents
  • SAUNDERS, Keith W.
Priority Data
17/357,47824.06.2021US
63/046,67930.06.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) CALIBRATION OF SAMPLING-BASED MULTIPLYING DELAY-LOCKED LOOP (MDLL)
(FR) ÉTALONNAGE DE BOUCLE À VERROUILLAGE DE RETARD MULTIPLICATRICE (MDLL) À BASE D'ÉCHANTILLONNAGE
Abstract
(EN) An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.
(FR) La présente invention concerne un appareil qui met en œuvre une boucle à verrouillage de retard multiplicatrice (MDLL) comprenant un échantillonneur à étalonner. Dans un aspect donné à titre d'exemple, un appareil comprend une MDLL et un dispositif d'étalonnage d'échantillonneur. La MDLL comprend un trajet d'anticipation à boucle verrouillée avec un échantillonneur, une sortie de commande, une entrée de rétroaction et une entrée de référence couplée à une source de signal de référence. La MDLL comprend également un VCO, un multiplexeur et un diviseur. Le VCO comprend une entrée de VCO, une sortie de VCO et une entrée de commande couplée à la sortie de commande. Le multiplexeur comprend une première entrée couplée à la source de signal de référence, une seconde entrée couplée à la sortie du VCO, et une sortie couplée à l'entrée du VCO. Le diviseur est couplé entre la sortie de VCO et l'entrée de rétroaction. Le dispositif d'étalonnage d'échantillonneur comprend une première entrée couplée à la source de signal de référence, une seconde entrée couplée à la sortie du VCO, et une sortie couplée à l'échantillonneur.
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