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1. WO2022005681 - THREE-DIMENSIONAL MEMORY DEVICE INCLUDING STAIRLESS WORD LINE CONTACT STRUCTURES FOR AND METHOD OF MAKING THE SAME

Publication Number WO/2022/005681
Publication Date 06.01.2022
International Application No. PCT/US2021/035466
International Filing Date 02.06.2021
IPC
H01L 21/768 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 21/311 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105After-treatment
311Etching the insulating layers
H01L 23/522 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Applicants
  • SANDISK TECHNOLOGIES LLC [US]/[US]
Inventors
  • TANAKA, Yoshinobu
  • ITO, Koichi
  • HASEGAWA, Hideaki
  • TOBIOKA, Akihiro
  • LEE, Sung Tae
Agents
  • RADOMSKY, Leon
  • COHN, Joanna
  • GAYOSO, Tony
  • GILL, Matthew
  • HANSEN, Robert
  • HONG, Mae
  • HUANG, Stephen
  • HYAMS, David
  • JOHNSON, Timothy
  • MAZAHERY, Benjamin
  • MELLO, John Paul
  • MILLER, Phillip
  • MURPHY, Timothy
  • NORRIS, Christine
  • O'BRIEN, Michelle
  • PARK, Byeongju
  • REYNOLDS, James
  • SHAUGHNESSY, Kevin
Priority Data
16/918,46301.07.2020US
16/918,49301.07.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) THREE-DIMENSIONAL MEMORY DEVICE INCLUDING STAIRLESS WORD LINE CONTACT STRUCTURES FOR AND METHOD OF MAKING THE SAME
(FR) DISPOSITIF DE MÉMOIRE TRIDIMENSIONNEL CONTENANT DES STRUCTURES DE CONTACT DE LIGNE DE MOTS SANS GRADIN ET SON PROCÉDÉ DE FABRICATION
Abstract
(EN) An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.
(FR) Un empilement alterné de couches isolantes et de couches de matériau sacrificiel est formé sur un substrat. Des ouvertures de mémoire et des ouvertures de support sont formées à travers l'empilement alterné. Des structures de remplissage des ouvertures de mémoire et des structures formant piliers de support sont respectivement formées dans les ouvertures de mémoire et dans les ouvertures de support. Des cavités de trous d'interconnexion s'étendant jusqu'à chacune des couches de matériau sacrificiel sont formées à travers l'empilement alterné sans former de surface en gradin dans l'empilement alterné. Les cavités des trous d'interconnexion peuvent être formées dans des zones ne chevauchant pas les structures formant piliers de support ou dans des zones contenant au moins une structure formant pilier de support. Des structures sacrificielles de remplissage des trous d'interconnexion sont formées dans les cavités des trous d'interconnexion. Les couches de matériau sacrificiel sont remplacées par des couches électroconductrices. Les structures sacrificielles de remplissage des trous d'interconnexion sont retirées. Une combinaison d'un espaceur diélectrique tubulaire et d'une structure de trou d'interconnexion de contact peut être formée dans les cavités des trous d'interconnexion.
Latest bibliographic data on file with the International Bureau