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1. WO2022005520 - SPACERLESS SOURCE CONTACT LAYER REPLACEMENT PROCESS AND THREE-DIMENSIONAL MEMORY DEVICE FORMED BY THE PROCESS

Publication Number WO/2022/005520
Publication Date 06.01.2022
International Application No. PCT/US2020/067134
International Filing Date 28.12.2020
IPC
H01L 21/768 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 21/285 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
283Deposition of conductive or insulating materials for electrodes
285from a gas or vapour, e.g. condensation
H01L 27/11529 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11526characterised by the peripheral circuit region
11529of memory regions comprising cell select transistors, e.g. NAND
H01L 27/11524 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11521characterised by the memory core region
11524with cell select transistors, e.g. NAND
H01L 27/11565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11565characterised by the top-view layout
CPC
G11C 5/025
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
G11C 5/06
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 21/76802
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
H01L 21/76877
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
H01L 27/11556
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11551characterised by three-dimensional arrangements, e.g. with cells on different height levels
11553with source and drain on different levels, e.g. with sloping channels
11556the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
1158with source and drain on different levels, e.g. with sloping channels
11582the channels comprising vertical portions, e.g. U-shaped channels
Applicants
  • SANDISK TECHNOLOGIES LLC [US]/[US]
Inventors
  • HINOUE, Tatsuya
Agents
  • RADOMSKY, Leon
  • COHN, Joanna
  • CONNOR, David
  • COUGHLIN, Timothy
  • GAYOSO, Tony
  • GILL, Matthew
  • HANSEN, Robert M.
  • HONG, Mae
  • HUANG, Stephen D.
  • HYAMS, David
  • JOHNSON, Timothy
  • LATHAM, Bryan
  • MAZAHERY, Benjamin
  • MELLO, John Paul
  • MURPHY, Timothy
  • NORRIS, Christine
  • O'BRIEN, Michelle
  • PARK, Byeongju
Priority Data
16/916,47630.06.2020US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) SPACERLESS SOURCE CONTACT LAYER REPLACEMENT PROCESS AND THREE-DIMENSIONAL MEMORY DEVICE FORMED BY THE PROCESS
(FR) PROCÉDÉ DE REMPLACEMENT DE COUCHE DE CONTACT DE SOURCE SANS SÉPARATEUR ET DISPOSITIF DE MÉMOIRE TRIDIMENSIONNEL FORMÉ PAR LE PROCÉDÉ
Abstract
(EN) In-process source-level material layers including a source-level sacrificial layer is formed over a substrate, and an alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory openings and backside openings are formed through the alternating stack and into the in-process source-level material layers. Memory opening fill structures are formed in the memory openings. A source cavity is formed by removing the source-level sacrificial layer by introducing an etchant through the backside openings, and a source contact layer in the source cavity. The backside openings are laterally expanded and are merged to form backside trenches. Remaining portions of the sacrificial material layers are replaced with electrically conductive layers through the respective backside trenches.
(FR) Des couches de matériau de niveau source en traitement comprenant une couche sacrificielle de niveau source sont formées sur un substrat, et un empilement alterné de couches isolantes et de couches de matériau sacrificiel est formé au-dessus. Des ouvertures de mémoire et des ouvertures arrière sont formées à travers l'empilement alterné et dans les couches de matériau de niveau source en traitement. Des structures de remplissage d'ouverture de mémoire sont formées dans les ouvertures de mémoire. Une cavité de source est formée par retrait de la couche sacrificielle de niveau source par introduction d'un agent de gravure à travers les ouvertures côté arrière, et d'une couche de contact de source dans la cavité de source. Les ouvertures arrière sont étendues latéralement et sont fusionnées pour former des tranchées arrière. Les parties restantes des couches de matériau sacrificiel sont remplacées par des couches électriquement conductrices à travers les tranchées côté arrière respectives.
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