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1. WO2022004804 - ELECTROSTATIC WITHSTAND VOLTAGE TESTING DEVICE AND ELECTROSTATIC WITHSTAND VOLTAGE TESTING METHOD

Publication Number WO/2022/004804
Publication Date 06.01.2022
International Application No. PCT/JP2021/024800
International Filing Date 30.06.2021
IPC
H01L 21/66 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
66Testing or measuring during manufacture or treatment
H01L 21/822 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
H01L 27/04 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
G01R 31/26 2020.1
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
26Testing of individual semiconductor devices
G01R 31/30 2006.1
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
30Marginal testing, e.g. by varying supply voltage
Applicants
  • 三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP]/[JP]
Inventors
  • 中西 浩平 NAKANISHI, Kohei
  • 金谷 雅夫 KANATANI, Masao
  • 安藤 慎一郎 ANDO, Shinichiro
Agents
  • 特許業務法人深見特許事務所 FUKAMI PATENT OFFICE, P.C.
Priority Data
2020-11558203.07.2020JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) ELECTROSTATIC WITHSTAND VOLTAGE TESTING DEVICE AND ELECTROSTATIC WITHSTAND VOLTAGE TESTING METHOD
(FR) DISPOSITIF DE TEST DE TENSION DE TENUE ÉLECTROSTATIQUE ET PROCÉDÉ DE TEST DE TENSION DE TENUE ÉLECTROSTATIQUE
(JA) 静電気耐圧試験装置および静電気耐圧試験方法
Abstract
(EN) A mounting substrate (8) has provided thereon a plurality of terminals (9a to 9c) and a conductor pattern, the conductor pattern being respectively electrically connected to a plurality of pins of a semiconductor device. An electrostatic withstand voltage testing device (100) is provided with: a metal plate (4) on which the mounting substrate (8) is mounted; a power supply (2) for supplying a voltage to the metal plate (4); an insulator (5) disposed between the metal plate (4) and the mounting substrate (8); a switch circuit (6) connected between the plurality of terminals (9a to 9d) and a ground wire; and a control unit (7) for controlling the switch circuit (6). The switch circuit (6) includes a plurality of first switches (6a to 6c) provided respectively corresponding to the plurality of terminals (9a to 9c) and configured to connect the corresponding terminals to the ground wire (24). The control unit (7), when discharging charge stored in the conductor pattern to the ground wire (24) via the semiconductor device, turns on at least one first switch selected from the plurality of first switches (6a to 6c).
(FR) Une pluralité de bornes (9a à 9c) et un motif conducteur se trouvent sur un substrat de montage (8), le motif conducteur étant respectivement connecté électriquement à une pluralité de broches d'un dispositif à semi-conducteurs. Un dispositif de test de tension de tenue électrostatique (100) est pourvu : d'une plaque métallique (4) sur laquelle le substrat de montage (8) est monté ; d'une alimentation électrique (2) permettant de fournir une tension à la plaque métallique (4) ; d'un isolant (5) disposé entre la plaque métallique (4) et le substrat de montage (8) ; d'un circuit de commutation (6) connecté entre la pluralité de bornes (9a à 9d) et un fil de masse ; et d'une unité de commande (7) permettant de commander le circuit de commutation (6). Le circuit de commutation (6) comprend une pluralité de premiers commutateurs (6a à 6c) qui correspondent respectivement à la pluralité de bornes (9a à 9c) et sont conçus pour connecter les bornes correspondantes au fil de masse (24). L'unité de commande (7), lors de la décharge d'une charge stockée dans le motif conducteur vers le fil de masse (24) par l'intermédiaire du dispositif à semi-conducteurs, met en marche au moins un premier commutateur choisi parmi la pluralité de premiers commutateurs (6a à 6c).
(JA) 実装基板(8)には、半導体デバイスの複数のピンとそれぞれ電気的に接続される複数の端子(9a~9c)および、導体パターンが設けられている。静電気耐圧試験装置(100)は、実装基板(8)が搭載される金属板(4)と、金属板(4)に電圧を印加するための電源(2)と、金属板(4)と実装基板(8)との間に配置される絶縁体(5)と、複数の端子(9a~9d)および接地配線の間に接続されるスイッチ回路(6)と、スイッチ回路(6)を制御する制御部(7)とを備える。スイッチ回路(6)は、複数の端子(9a~9c)にそれぞれ対応して設けられ、対応する端子を接地配線(24)に接続するように構成された複数の第1のスイッチ(6a~6c)を含む。制御部(7)は、導体パターンに蓄えられた電荷を、半導体デバイスを介して接地配線(24)に放電するときに、複数の第1のスイッチ(6a~6c)から選択した少なくとも1つの第1のスイッチをオンする。
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