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1. WO2022004160 - SEMICONDUCTOR DEVICE AND IMAGING DEVICE

Publication Number WO/2022/004160
Publication Date 06.01.2022
International Application No. PCT/JP2021/018582
International Filing Date 17.05.2021
IPC
H01L 29/78 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
H01L 21/336 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
H01L 27/146 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144Devices controlled by radiation
146Imager structures
H04N 5/369 2011.1
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
30Transforming light or analogous information into electric information
335using solid-state image sensors
369SSIS architecture; Circuitry associated therewith
H04N 5/374 2011.1
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
30Transforming light or analogous information into electric information
335using solid-state image sensors
369SSIS architecture; Circuitry associated therewith
374Addressed sensors, e.g. MOS or CMOS sensors
Applicants
  • ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP]/[JP]
Inventors
  • ▲高▼柳 良平 TAKAYANAGI Ryohei
Agents
  • 田中 秀▲てつ▼ TANAKA Hidetetsu
  • 小林 龍 KOBAYASHI Toru
  • 森 哲也 MORI Tetsuya
Priority Data
2020-11107429.06.2020JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND IMAGING DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET DISPOSITIF D'IMAGERIE
(JA) 半導体装置及び撮像装置
Abstract
(EN) The present invention provides a semiconductor device and imaging device capable of suppressing a short channel effect. The semiconductor device comprises a semiconductor substrate and a transistor provided to the semiconductor substrate. The transistor includes: a main surface; a semiconductor region having a first side surface which intersects the main surface; a gate insulation film provided on the semiconductor region; a gate electrode provided on the gate insulation film; a channel region which is covered by the gate insulation film and the gate electrode in the semiconductor region; and a source region and a drain region of a first conductivity type and adjoining the channel region. In a plan view from the normal direction of the main surface, the semiconductor region includes a first site which extends in a first direction and a second site which extends in a second direction intersecting the first direction from the first site. The channel region includes a first channel region present on the main surface and a second channel region present on the first side surface and extending in the depth direction of the semiconductor region.
(FR) La présente invention concerne un dispositif à semi-conducteur et un dispositif d'imagerie capables de supprimer un effet de canal court. Le dispositif à semi-conducteur comprend un substrat semi-conducteur, et un transistor disposé sur le substrat semi-conducteur. Le transistor comprend : une surface principale ; une région semi-conductrice ayant une première surface latérale qui coupe la surface principale ; un film d'isolation de grille disposé sur la région semi-conductrice ; une électrode de grille disposée sur le film d'isolation de grille ; une région de canal qui est recouverte par le film d'isolation de grille et l'électrode de grille dans la région semi-conductrice ; et une région de source et une région de drain d'un premier type de conductivité et adjacentes à la région de canal. Dans une vue en plan à partir de la direction normale de la surface principale, la région semi-conductrice comprend un premier site qui s'étend dans une première direction et un second site qui s'étend dans une seconde direction croisant la première direction à partir du premier site. La région de canal comprend une première région de canal présente sur la surface principale et une seconde région de canal présente sur la première surface latérale et s'étendant dans le sens de la profondeur de la région semi-conductrice.
(JA) 短チャネル効果を抑制可能な半導体装置及び撮像装置を提供する。半導体装置は、半導体基板と、半導体基板に設けられたトランジスタと、を備える。トランジスタは、主面と、主面と交差する第1側面とを有する半導体領域と、半導体領域上に設けられたゲート絶縁膜と、ゲート絶縁膜上に設けられたゲート電極と、半導体領域においてゲート絶縁膜及びゲート電極で覆われたチャネル領域と、チャネル領域に隣接する第1導電型のソース領域及びドレイン領域と、を有する。主面の法線方向からの平面視で、半導体領域は、 第1方向に延設された第1部位と、第1部位から第1方向と交差する第2方向に延設された第2部位と、を有する。チャネル領域は、主面に存在する第1チャネル領域と、第1側面に存在し、半導体領域の深さ方向に延びた第2チャネル領域と、を有する。
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