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1. WO2022001486 - SEMICONDUCTOR STRUCTURE TREATMENT METHOD AND FORMATION METHOD

Publication Number WO/2022/001486
Publication Date 06.01.2022
International Application No. PCT/CN2021/095582
International Filing Date 24.05.2021
IPC
H01L 21/02 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/3065 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
3065Plasma etching; Reactive-ion etching
H01L 21/308 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
308using masks
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 郗宁 XI, Ning
Agents
  • 上海晨皓知识产权代理事务所(普通合伙) SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP
Priority Data
202010634483.602.07.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) SEMICONDUCTOR STRUCTURE TREATMENT METHOD AND FORMATION METHOD
(FR) PROCÉDÉ DE TRAITEMENT DE STRUCTURE SEMI-CONDUCTRICE ET PROCÉDÉ DE FORMATION
(ZH) 半导体结构的处理方法及形成方法
Abstract
(EN) A semiconductor structure treatment method and formation method. The semiconductor structure treatment method comprises: providing a semiconductor substrate (111), the semiconductor substrate (111) being provided with feature portions (112) thereon, the depth-to-width ratio of the feature portions (112) being greater than a preset depth-to-width ratio, and mask layers (200) being disposed on the tops of the feature portions (112); performing ashing treatment on a semiconductor structure, the semiconductor structure comprising the semiconductor substrate (111), the feature portions (112), and the mask layers (200); performing washing treatment on the semiconductor structure; performing drying treatment on the semiconductor structure; and removing the mask layers (200). During the drying treatment, one mask layer (200) in at least one group of adjacent mask layers (200) is inclined towards the direction of the adjacent mask layer (200); moreover, the distance between the inclined mask layer (200) and the adjacent mask layer (200) after the drying treatment is less than the distance between the two before the drying treatment.
(FR) La présente invention concerne un procédé de traitement de structure semi-conductrice et un procédé de formation. Le procédé de traitement de structure semi-conductrice comprend : la fourniture d'un substrat semi-conducteur (111) pourvu de parties de caractéristique (112) sur lui, le rapport profondeur/largeur des parties caractéristiques (112) étant supérieur à un rapport profondeur-largeur prédéfini, et des couches de masque (200) étant disposés sur les parties supérieures des parties caractéristiques (112) ; la réalisation d'un traitement de calcination sur une structure semi-conductrice, la structure semi-conductrice comprenant le substrat semi-conducteur (111), les parties de caractéristique (112) et les couches de masque (200) ; la réalisation d'un traitement de lavage sur la structure de semi-conducteur ; la réalisation d'un traitement de séchage sur la structure de semi-conducteur ; et le retrait des couches de masque (200). Pendant le traitement de séchage, une couche de masque (200) dans au moins un groupe de couches de masque adjacentes (200) est inclinée vers la direction de la couche de masque adjacente (200) ; de plus, la distance entre la couche de masque inclinée (200) et la couche de masque adjacente (200) après le traitement de séchage est inférieure à la distance entre les deux avant le traitement de séchage.
(ZH) 一种半导体结构的处理方法及形成方法,该半导体结构的处理方法包括:提供半导体基底(111),半导体基底(111)上设置有特征部(112),特征部(112)的深宽比大于预设深宽比,特征部(112)顶部设置有掩膜层(200);对半导体结构进行灰化处理,半导体结构包括半导体基底(111)、特征部(112)以及掩膜层(200);对半导体结构进行清洗处理;对半导体结构进行干燥处理;去除掩膜层(200);在干燥处理过程中,至少相邻的一组掩膜层(200)中一掩膜层(200)向相邻掩膜层(200)的方向倾斜,且在干燥处理之后,倾斜的掩膜层(200)与相邻掩膜层(200)的间距小于在干燥处理之前二者的间距。
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