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1. WO2022001442 - THIN FILM TRANSISTOR, GATE ROW DRIVING CIRCUIT AND ARRAY SUBSTRATE

Publication Number WO/2022/001442
Publication Date 06.01.2022
International Application No. PCT/CN2021/094512
International Filing Date 19.05.2021
IPC
H01L 29/786 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
H01L 29/423 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
H01L 29/417 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
41characterised by their shape, relative sizes or dispositions
417carrying the current to be rectified, amplified or switched
H01L 27/12 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
Applicants
  • 京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN]/[CN]
Inventors
  • 王利忠 WANG, Lizhong
  • 宁策 NING, Ce
  • 胡合合 HU, Hehe
  • 周天民 ZHOU, Tianmin
  • 宋吉鹏 SONG, Jipeng
Agents
  • 北京银龙知识产权代理有限公司 DRAGON INTELLECTUAL PROPERTY LAW FIRM
Priority Data
202010598519.X28.06.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) THIN FILM TRANSISTOR, GATE ROW DRIVING CIRCUIT AND ARRAY SUBSTRATE
(FR) TRANSISTOR À COUCHES MINCES, CIRCUIT D'ATTAQUE DE RANGÉE DE GRILLE ET SUBSTRAT DE RÉSEAU
(ZH) 一种薄膜晶体管、栅极行驱动电路及阵列基板
Abstract
(EN) The present disclosure provides a thin film transistor, a gate row driving circuit and an array substrate. The thin film transistor comprises: a source, comprising source wirings and a plurality of source branches; a drain, comprising drain wirings and a plurality of drain branches; a gate; and a semiconductor layer, comprising a plurality of semiconductor branches. The plurality of source branches and the plurality of drain branches are in contact with the plurality of semiconductor branches, and are divided into a plurality of units; the source wirings and the drain wirings are arranged in parallel and spaced apart, the number m of one of the source wirings and the drain wirings is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1; and the plurality of units are arranged in at least two unit rows, the source branches in each unit row are connected to the same source wiring, and the drain branches in each unit row are connected to the same drain wiring. The thin film transistor, the gate row driving circuit and the array substrate provided in the present disclosure solve the problem of heat accumulation caused by the highly aggregated arrangement of the source and drain branches of the thin film transistor.
(FR) L’invention concerne un transistor à couches minces, un circuit d'attaque de rangée de grille et un substrat de réseau. Le transistor à couches minces comprend : une source, comprenant des câblages de source et une pluralité de branches de source ; un drain, comprenant des câblages de drain et une pluralité de branches de drain ; une grille ; et une couche semi-conductrice, comprenant une pluralité de branches de semi-conducteur. La pluralité de branches de source et la pluralité de branches de drain sont en contact avec la pluralité de branches de semi-conducteur, et sont divisées en une pluralité d'unités ; les câblages de source et les câblages de drain étant agencés en parallèle et espacés, le nombre m d'un élément parmi les câblages de source et les câblages de drain est un nombre entier supérieur ou égal à 2, et le nombre n de l'autre est un nombre entier supérieur ou égal à 1 ; et la pluralité d'unités sont disposées en au moins deux rangées unitaires, les branches de source dans chaque rangée d'unités sont connectées au même câblage de source, et les branches de drain dans chaque rangée d'unités sont connectées au même câblage de drain. Le transistor à couches minces, le circuit d'attaque de rangée de grille et le substrat de réseau décrits dans la présente invention résolvent le problème de l'accumulation de chaleur provoquée par l'agencement hautement agrégé des branches de source et de drain du transistor à couches minces.
(ZH) 本公开提供一种薄膜晶体管、栅极行驱动电路及阵列基板,该薄膜晶体管包括:源极,包括源极走线和多个源极分支;漏极,包括漏极走线和多个漏极分支;栅极;半导体层,包括多个半导体分支;多个源极分支、多个漏极分支与多个半导体分支接触,分为多个单元;源极走线和漏极走线平行间隔设置,源极走线和漏极走线中的一个的数量m为大于或等于2的整数,另一个的数量n为大于或等于1的整数;多个单元排列为至少两个单元行,每一单元行内的源极分支连接同一根源极走线,每一单元行内的漏极分支连接同一根漏极走线。本公开提供的薄膜晶体管、栅极行驱动电路及阵列基板,解决薄膜晶体管源、漏极分支高聚集布置导致热量聚集的问题。
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