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1. WO2022000438 - DRAM CHIP THREE-DIMENSIONAL INTEGRATION SYSTEM AND MANUFACTURING METHOD THEREFOR

Publication Number WO/2022/000438
Publication Date 06.01.2022
International Application No. PCT/CN2020/099997
International Filing Date 02.07.2020
IPC
H01L 23/48 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
H01L 21/768 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 21/52 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
52Mounting semiconductor bodies in containers
CPC
H01L 21/52
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
52Mounting semiconductor bodies in containers
H01L 21/76898
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76898formed through a semiconductor substrate
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 23/481
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
481Internal lead connections, e.g. via connections, feedthrough structures
H01L 25/0652
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
03all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/00
0652the devices being arranged next and on each other, i.e. mixed assemblies
Applicants
  • 复旦大学 FUDAN UNIVERSITY [CN]/[CN]
  • 上海集成电路制造创新中心有限公司 SHANGHAI INTEGRATED CIRCUIT MANUFACTURING INNOVATION CENTER CO., LTD [CN]/[CN]
Inventors
  • 朱宝 ZHU, Bao
  • 陈琳 CHEN, Lin
  • 孙清清 SUN, Qingqing
  • 张卫 ZHANG, Wei
Agents
  • 北京得信知识产权代理有限公司 BEIJING TRUSTED INTELLECTUAL PROPERTY AGENCY LTD
Priority Data
202010620300.530.06.2020CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) DRAM CHIP THREE-DIMENSIONAL INTEGRATION SYSTEM AND MANUFACTURING METHOD THEREFOR
(FR) SYSTÈME D'INTÉGRATION TRIDIMENSIONNELLE DE PUCE DRAM ET SON PROCÉDÉ DE FABRICATION
(ZH) 一种DRAM芯片三维集成系统及其制备方法
Abstract
(EN) Disclosed in the present invention are a DRAM chip three-dimensional integration system and a manufacturing method therefor. Said method comprises: forming, by etching, several trench structures on the front and back sides of a silicon wafer; then, forming, by etching, a TSV structure between two vertically opposite trenches for electrical connection; next, placing DRAM chips in the trenches, and using a copper-copper bonding method to electrically connect the chips in the vertical direction to the TSV structures; and finally, forming a redistribution layer to electrically connect the chips in the horizontal direction. The present invention can fully utilize silicon materials, and can avoid problems such as warpage and deformation of interposers. In addition, as the chips are placed in the trenches, the overall package thickness will not be increased, and the chips can be protected from external impact.
(FR) Un système d'intégration tridimensionnelle de puce DRAM et son procédé de fabrication sont divulgués dans la présente invention. Ledit procédé consiste à : former, par gravure, plusieurs structures de tranchée sur les côtés avant et arrière d'une tranche de silicium; ensuite, former, par gravure, une structure TSV entre deux tranchées opposées verticalement aux fins d'une connexion électrique; ensuite, placer des puces DRAM dans les tranchées, et utiliser un procédé de liaison cuivre-cuivre pour connecter électriquement les puces, dans la direction verticale, aux structures TSV; et enfin, former une couche de redistribution pour connecter électriquement les puces dans la direction horizontale. La présente invention peut pleinement utiliser des matériaux de silicium, et peut éviter des problèmes tels que le gauchissement et la déformation d'interposeurs. De plus, lorsque les puces sont placées dans les tranchées, l'épaisseur globale du boîtier n'est pas accrue, et les puces peuvent être protégées contre un impact externe.
(ZH) 本发明公开了一种DRAM芯片三维集成系统及其制备方法。在硅片正反面刻蚀出若干个沟槽结构;然后,在上下相对的两个沟槽之间刻蚀出TSV结构进行电气连通;接着,在沟槽内放置DRAM芯片,并采用铜-铜键合的方式使得垂直方向上芯片与TSV结构电气连通;最后进行重布线,使得水平方向上的芯片之间电气连通。本发明能够充分利用硅材料,而且可以避免转接板出现翘曲、变形等问题。此外,将芯片放置在沟槽内,既不会增大整体封装厚度,又能保护芯片不会受到外力冲击。
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