Processing

Please wait...

Settings

Settings

Goto Application

1. WO2021066893 - MULTI-PATH PACKET DESCRIPTOR DELIVERY SCHEME

Publication Number WO/2021/066893
Publication Date 08.04.2021
International Application No. PCT/US2020/036851
International Filing Date 09.06.2020
IPC
H04L 12/937 2013.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
70Packet switching systems
931Switch fabric architecture
937Switch control, e.g. arbitration
H04L 12/833 2013.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
70Packet switching systems
801Flow control or congestion control
811Bitrate adaptation in active flows
833Marking packets or altering packet priority upon congestion or for congestion prevention
H04L 12/707 2013.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
70Packet switching systems
701Routing or path finding
703Route fault prevention or recovery, e.g. rerouting, route redundancy, virtual router redundancy protocol or hot standby router protocol
707using path redundancy
H04L 12/933 2013.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
70Packet switching systems
931Switch fabric architecture
933Switch core, e.g. crossbar, shared memory or shared medium
H04L 12/935 2013.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
70Packet switching systems
931Switch fabric architecture
935Switch interfaces, e.g. port details
H04L 12/879 2013.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
70Packet switching systems
801Flow control or congestion control
861Packet buffering or queuing arrangements; Queue scheduling
879Single buffer operations, e.g. buffer pointers or buffer descriptors
CPC
H04L 47/6255
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
47Traffic regulation in packet switching networks
50Queue scheduling
62General aspects
625Other criteria for service slot or service order
6255queue load conditions, e.g. longest queue first
H04L 49/901
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
49Packet switching elements
90Queuing arrangements
901Storage descriptor, e.g. read or write pointers
H04L 67/2842
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
67Network-specific arrangements or communication protocols supporting networked applications
28for the provision of proxy services, e.g. intermediate processing or storage in the network
2842for storing data temporarily at an intermediate stage, e.g. caching
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • SOUTHWORTH, Robert
  • PAPADANTONAKIS, Karl
  • NYSTROEM, Mika
  • SRINIVASAN, Arvind
  • ARDITTI ILITZKY, David
  • DAMA, Jonathan
Agents
  • CHOI, Glen B.
  • ANDERSON, Vincent A.
Priority Data
16/727,54326.12.2019US
62/908,49030.09.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MULTI-PATH PACKET DESCRIPTOR DELIVERY SCHEME
(FR) SCHÉMA DE DISTRIBUTION DE DESCRIPTEUR DE PAQUET À TRAJETS MULTIPLES
Abstract
(EN)
Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.
(FR)
Des exemples décrivent l'utilisation de multiples schémas de distribution de métadonnées pour fournir des étiquettes qui décrivent des paquets à un groupe de ports de sortie. Une étiquette, qui est plus petite qu'un paquet, peut être associée à un paquet. L'étiquette peut être stockée dans une mémoire, en tant qu'un groupe avec d'autres étiquettes, et l'étiquette peut être distribuée à une file d'attente associée à un port de sortie. Les paquets reçus au niveau d'un port d'entrée peuvent être sous une forme non entrelacée pour réduire le sous-débordement et fournir un passage vers un port de sortie. Une mémoire partagée peut être attribuée pour stocker des paquets reçus au niveau d'un seul port d'entrée, ou partagée pour stocker des paquets provenant de multiples ports d'entrée.
Latest bibliographic data on file with the International Bureau