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1. WO2021066100 - DRIVING METHOD OF SYNAPSE CIRCUIT

Publication Number WO/2021/066100
Publication Date 08.04.2021
International Application No. PCT/JP2020/037440
International Filing Date 01.10.2020
IPC
H01L 43/08 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
08Magnetic-field-controlled resistors
H01L 21/8239 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
H01L 27/105 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
H01L 21/8244 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8244Static random access memory structures (SRAM)
H01L 27/11 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
11Static random access memory structures
H01L 29/82 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
82controllable by variation of the magnetic field applied to the device
CPC
G06N 3/04
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
G06N 3/063
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
G11C 11/16
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
G11C 11/54
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
54using elements simulating biological cells, e.g. neuron
H01L 21/8239
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8239Memory structures
H01L 27/105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
Applicants
  • 国立大学法人東北大学 TOHOKU UNIVERSITY [JP]/[JP]
Inventors
  • 馬 奕涛 MA Yitao
  • 遠藤 哲郎 ENDOH Tetsuo
Agents
  • 特許業務法人ドライト国際特許事務所 DORAIT IP LAW FIRM
Priority Data
2019-18254902.10.2019JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) DRIVING METHOD OF SYNAPSE CIRCUIT
(FR) PROCÉDÉ DE COMMANDE DE CIRCUIT SYNAPTIQUE
(JA) シナプス回路の駆動方法
Abstract
(EN)
Provided is a driving method of a simplified synapse circuit. When a first pre-spike pulse precedes a first post-spike pulse, a second pre-spike pulse from an input circuit 20a is used as a time window in which writing of a connection weight is permitted, and the first post-spike pulse from a neuron circuit 17 is used as a writing pulse of a writing timing control for the connection weight. When the first post-spike pulse precedes the first pre-spike pulse, a second post-spike pulse from the neuron circuit 17 is used as a time window, and the first pre-spike pulse from the input circuit 20a is used as a writing pulse. The second pre-spike pulse and the second post-spike pulse are respectively synchronized with the first pre-spike pulse and the first post-spike pulse to be output.
(FR)
L’invention concerne un procédé de commande de circuit synaptique simplifié. Lorsqu'une première impulsion de pré-pic précède une première impulsion de post-pic, une seconde impulsion de pré-pic provenant d'un circuit d'entrée 20a est utilisée en tant que fenêtre temporelle dans laquelle l'écriture d'un poids de connexion est permise, et la première impulsion de post-pic provenant d'un circuit neuronal 17 est utilisée en tant qu'impulsion d'écriture d'une commande de synchronisation d'écriture pour le poids de connexion. Lorsque la première impulsion de post-pic précède la première impulsion de pré-pic, une seconde impulsion de post-pic provenant du circuit neuronal 17 est utilisée en tant que fenêtre de temps, et la première impulsion de pré-pic provenant du circuit d'entrée 20a est utilisée en tant qu'impulsion d'écriture. La seconde impulsion de pré-pic et la seconde impulsion de post-pic sont respectivement synchronisées avec la première impulsion de pré-pic et la première impulsion de post-pic à délivrer en sortie.
(JA)
簡単化されたシナプス回路の駆動方法を提供する。第1ポストスパイクパルスに対して第1プレスパイクパルスが先行する場合では、結合荷重の書き込みを許容する時間窓として入力回路20aからの第2プレスパイクパルスを用い、結合荷重の書き込みタイミングの制御の書き込みパルスとしてニューロン回路17からの第1ポストスパイクパルスを用いる。第1プレスパイクパルスに対して第1ポストスパイクパルスが先行する場合には、時間窓としてニューロン回路17からの第2ポストスパイクパルスを用い、書き込みパルスとして、入力回路20aからの第1プレスパイクパルスを用いる。第2プレスパイクパルスは、第2ポストスパイクパルスは、それぞれ第1プレスパイクパルス、第1ポストスパイクパルスに同期して出力される。
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