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1. WO2021062178 - BIT WIDTH RECONFIGURATION USING A SHADOW-LATCH CONFIGURED REGISTER FILE

Publication Number WO/2021/062178
Publication Date 01.04.2021
International Application No. PCT/US2020/052756
International Filing Date 25.09.2020
IPC
G06F 9/30 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
CPC
G06F 9/30014
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
3001Arithmetic instructions
30014with variable precision
G06F 9/30101
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
30101Special purpose registers
G06F 9/30116
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
30105Register structure
30116Shadow registers, e.g. coupled registers, not forming part of the register space
G06F 9/3013
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
3012Organisation of register space, e.g. banked or distributed register file
3013according to data content, e.g. floating-point registers, address registers
G06F 9/30138
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
3012Organisation of register space, e.g. banked or distributed register file
30138Extension of register space, e.g. register cache
G06F 9/30189
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30181Instruction operation extension or modification
30189according to execution mode, e.g. mode flag
Applicants
  • ADVANCED MICRO DEVICES, INC. [US]/[US]
Inventors
  • NAIR, Arun A.
  • BAUMGARTNER, Todd
  • ESTLICK, Michael
  • SWANSON, Erik
Agents
  • DAVIDSON, Ryan S.
Priority Data
16/585,81727.09.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) BIT WIDTH RECONFIGURATION USING A SHADOW-LATCH CONFIGURED REGISTER FILE
(FR) RECONFIGURATION DE NOMBRE DE BITS À L'AIDE D'UN FICHIER DE REGISTRES CONFIGURÉ AVEC VERROUS FANTÔMES
Abstract
(EN)
A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadowlatch configured floating point register file to perform bit width reconfiguration. The shadow-latch configured floating point register file includes a plurality of regular latches and a plurality of shadow latches for storing data that is to be either read from or written to the shadow latches. The bit width reconfiguration enables the floating point unit that operates at the second bit width to operate on the instruction set received at the first bit width.
(FR)
L'invention concerne un processeur qui comprend un frontal ayant un ensemble d'instructions qui fonctionne à un premier nombre de bits et une unité à virgule flottante couplée pour recevoir l'ensemble d'instructions dans le processeur qui fonctionne au premier nombre de bits. L'unité à virgule flottante fonctionne à un second nombre de bits et, sur la base d'une évaluation de nombre de bits de l'ensemble d'instructions fourni à l'unité à virgule flottante, l'unité à virgule flottante utilise un fichier de registres à virgule flottante configuré avec verrous fantômes pour effectuer une reconfiguration de nombre de bits. Le fichier de registres à virgule flottante configuré avec verrous fantômes comprend une pluralité de verrous ordinaires et une pluralité de verrous fantômes pour stocker des données qui doivent être lues ou écrites dans les verrous fantômes. La reconfiguration de nombre de bits permet à l'unité à virgule flottante qui fonctionne au second nombre de bits de fonctionner sur l'ensemble d'instructions reçu au premier nombre de bits.
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