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1. WO2021061514 - PROCESSOR AND INTERRUPT CONTROLLER THEREIN

Publication Number WO/2021/061514
Publication Date 01.04.2021
International Application No. PCT/US2020/051446
International Filing Date 18.09.2020
IPC
G06F 13/18 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
18with priority control
G06F 13/20 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
G06F 13/24 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
24using interrupt
G06F 13/26 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
24using interrupt
26with priority control
G06F 15/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
CPC
G06F 13/26
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
24using interrupt
26with priority control
G06F 13/366
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
36for access to common bus or bus system
362with centralised access control
366using a centralised polling arbiter
G06F 15/7807
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
G06F 9/4818
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
4806Task transfer initiation or dispatching
4812by interrupt, e.g. masked
4818Priority circuits therefor
Applicants
  • ALIBABA GROUP HOLDING LIMITED
Inventors
  • ZHAO, Chaojun
  • JIANG, Tao
Agents
  • MURABITO, Anthony, C.
Priority Data
201910912610.125.09.2019CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PROCESSOR AND INTERRUPT CONTROLLER THEREIN
(FR) PROCESSEUR ET CONTRÔLEUR D'INTERRUPTION EN SON SEIN
Abstract
(EN)
The present invention discloses an interrupt controller, including: a sampling unit adapted to receive interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts; and a priority arbitration unit adapted to classify the received various interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, segment by segment, an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as an to-be-responded-to interrupt. The present invention further discloses a processor including the interrupt controller, and a system-on-chip.
(FR)
La présente invention concerne un contrôleur d'interruption, comprenant : une unité d'échantillonnage conçue pour recevoir des interruptions en provenance de diverses sources d'interruption couplées au contrôleur d'interruption et effectuer un échantillonnage sur les diverses interruptions reçues ; et une unité d'arbitrage de priorités conçue pour classer les diverses interruptions reçues en une pluralité de segments d'interruption, chaque segment d'interruption comprenant une ou plusieurs interruptions échantillonnées, et déterminer, segment par segment, une interruption présentant la priorité la plus élevée dans un segment sélectionné, jusqu'à ce qu'une interruption avec la priorité la plus élevée parmi toutes les interruptions soit identifiée par l'intermédiaire d'un arbitrage et utilisée en tant qu'interruption à laquelle l'on doit répondre. La présente invention concerne en outre un processeur comprenant le contrôleur d'interruption et un système sur puce.
Also published as
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