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1. WO2021061498 - SRAM LOW-POWER WRITE DRIVER

Publication Number WO/2021/061498
Publication Date 01.04.2021
International Application No. PCT/US2020/051327
International Filing Date 17.09.2020
IPC
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 11/419 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417for memory cells of the field-effect type
419Read-write circuits
G11C 29/32 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
08Functional testing, e.g. testing during refresh, power-on self testing or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing
18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
30Accessing single arrays
32Serial access; Scan testing
CPC
G11C 11/419
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
417for memory cells of the field-effect type
419Read-write [R-W] circuits
G11C 2029/3202
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
30Accessing single arrays
3202Scan chain
G11C 29/32
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
30Accessing single arrays
32Serial access; Scan testing
G11C 7/1087
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
1087Data input latches
G11C 7/1096
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
1096Write circuits, e.g. I/O line write drivers
H03K 3/35625
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
353by the use, as active elements, of field-effect transistors with internal or external positive feedback
356Bistable circuits
3562of the master-slave type
35625using complementary field-effect transistors
Applicants
  • QUALCOMM INCORPORATED [US]/[US]
Inventors
  • JUNG, Changho
  • JUNG, Chulmin
  • DADABHOY, Percy
Agents
  • HALLMAN, Jonathan W.
  • WEBB, Gregory P.
  • KELTON, Thomas W.
  • CHEN, Tom
  • MICHELSON, Gregory J.
  • WELCH, Henry L.
  • FOWLES, Adam
  • NGUYEN, Thuc B.
  • EDWARDS, Gary J.
  • LI, Eric
  • HUH, Gregory
Priority Data
16/911,31324.06.2020US
62/906,67826.09.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SRAM LOW-POWER WRITE DRIVER
(FR) PILOTE D'ÉCRITURE DE FAIBLE PUISSANCE SRAM
Abstract
(EN)
A memory is provided with a pre-charge circuit/write driver that pre-charges a bit line in a bit line pair responsive to a master latch output signal from a master latch in a data buffer. A slave latch associated with the master latch is prevented from becoming open by a clock controller during write operations for the memory.
(FR)
Une mémoire comprend un circuit de pré-charge/pilote d'écriture qui précharge une ligne de bits dans une paire de lignes de bits en réponse à un signal de sortie de verrou maître provenant d'un verrou maître dans un tampon de données. Un verrou esclave associé au verrou maître est empêché de s'ouvrir par un contrôleur d'horloge pendant des opérations d'écriture pour la mémoire.
Latest bibliographic data on file with the International Bureau