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1. WO2021061224 - ENABLING EARLY EXECUTION OF MOVE-IMMEDIATE INSTRUCTIONS HAVING VARIABLE IMMEDIATE VALUE SIZES IN PROCESSOR-BASED DEVICES

Publication Number WO/2021/061224
Publication Date 01.04.2021
International Application No. PCT/US2020/038270
International Filing Date 18.06.2020
IPC
G06F 9/30 2018.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 2018.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
CPC
G06F 9/30032
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
30032Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
G06F 9/30123
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
3012Organisation of register space, e.g. banked or distributed register file
30123according to context, e.g. thread buffers
G06F 9/3013
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
3012Organisation of register space, e.g. banked or distributed register file
3013according to data content, e.g. floating-point registers, address registers
G06F 9/30167
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30145Instruction analysis, e.g. decoding, instruction word fields
3016Decoding the operand specifier, e.g. specifier format
30167of immediate specifier, e.g. constants
G06F 9/3832
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3824Operand accessing
383Operand prefetching
3832Value prediction for operands; operand history buffers
G06F 9/384
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3838Dependency mechanisms, e.g. register scoreboarding
384Register renaming
Applicants
  • MICROSOFT TECHNOLOGY LICENSING, LLC [US]/[US]
Inventors
  • PRIYADARSHI, Shivam
  • PERAIS, Arthur
  • KOTHINTI NARESH, Vignyan Reddy
  • TEKMEN, Yusuf Cagatay
  • AL SHEIKH, Rami Mohammad
  • SMITH, Rodney Wayne
Agents
  • SWAIN, Cassandra T.
  • BARKER, Doug
  • CHATTERJEE, Aaron C.
  • CHEN, Wei-Chen Nicholas
  • CHOI, Daniel
  • CHURNA, Timothy
  • DINH, Phong
  • EVANS, Patrick
  • GABRYJELSKI, Henry
  • GUPTA, Anand
  • HINOJOSA-SMITH, Brianna L.
  • HWANG, William C.
  • JARDINE, John S.
  • LEE, Sunah
  • LEMMON, Marcus
  • MARQUIS, Thomas
  • MEYERS, Jessica
  • ROPER, Brandon
  • SPELLMAN, Steven
  • SULLIVAN, Kevin
  • WALKER, Matt
  • WIGHT, Stephen A.
  • WISDOM, Gregg
  • WONG, Ellen
  • WONG, Thomas S.
  • ZHANG, Hannah
  • TRAN, Kimberly
Priority Data
16/582,00825.09.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ENABLING EARLY EXECUTION OF MOVE-IMMEDIATE INSTRUCTIONS HAVING VARIABLE IMMEDIATE VALUE SIZES IN PROCESSOR-BASED DEVICES
(FR) ACTIVATION D'EXÉCUTION PRÉCOCE D'INSTRUCTIONS DE DÉPLACEMENT IMMÉDIAT AYANT DES TAILLES DE VALEURS IMMÉDIATES VARIABLES DANS DES DISPOSITIFS BASÉS SUR PROCESSEUR
Abstract
(EN)
Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices is disclosed. In one exemplary embodiment, a processor-based device provides a move-immediate logic circuit that detects a move-immediate instruction comprising an immediate value and a destination register. For frequently encountered immediate values, the move-immediate logic circuit allocates a physical register from an immediate physical register file (IPRF), and writes an IPRF tag corresponding to the allocated IPRF register into a most-recent mapping table (MRT) entry for the destination register. Subsequent move-immediate instructions embedding the same immediate value, as well as other dependent instructions, may then obtain the immediate value from the IPRF register by accessing the MRT entry. Additionally, the PE provides a frequent immediate table (FIT) for tracking occurrences of immediate values, and allocates IPRF registers for a given immediate value only when a count of occurrences of that immediate value exceeds a FIT threshold.
(FR)
La présente invention concerne l'activation de l'exécution précoce d'instructions de déplacement immédiat ayant des tailles de valeurs immédiates variables dans des dispositifs basés sur processeur. Selon un mode de réalisation donné à titre d'exemple, un dispositif basé sur processeur fournit un circuit logique de déplacement immédiat qui détecte une instruction de déplacement immédiat comprenant une valeur immédiate et un registre de destination. Pour des valeurs immédiates rencontrées fréquemment, le circuit logique de déplacement immédiat attribue un registre physique à partir d'un fichier de registre physique immédiat (IPRF), et écrit une étiquette IPRF correspondant au registre IPRF attribué dans une entrée, de table de mappage la plus récente (MRT), pour le registre de destination. Des instructions ultérieures de déplacement immédiat intégrant la même valeur immédiate, ainsi que d'autres instructions dépendantes, peuvent ensuite obtenir la valeur immédiate à partir du registre IPRF en accédant à l'entrée de MRT. De plus, le PE fournit une table immédiate fréquente (FIT) pour suivre des occurrences de valeurs immédiates, et attribue des registres IPRF pour une valeur immédiate donnée uniquement lorsqu'un nombre d'occurrences de cette valeur immédiate dépasse un seuil FIT.
Also published as
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