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1. WO2021056515 - THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Publication Number WO/2021/056515
Publication Date 01.04.2021
International Application No. PCT/CN2019/108895
International Filing Date 29.09.2019
IPC
H01L 27/1157 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11568characterised by the memory core region
1157with cell select transistors, e.g. NAND
CPC
H01L 21/0217
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02107Forming insulating materials on a substrate
02109characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
02112characterised by the material of the layer
02123the material containing silicon
0217the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
H01L 21/0228
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02107Forming insulating materials on a substrate
02225characterised by the process for the formation of the insulating layer
0226formation by a deposition process
02263deposition from the gas or vapour phase
02271deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
0228deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
H01L 21/02532
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02518Deposited layers
02521Materials
02524Group 14 semiconducting materials
02532Silicon, silicon germanium, germanium
H01L 21/0262
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02612Formation types
02617Deposition types
0262Reduction or decomposition of gaseous compounds, e.g. CVD
H01L 21/30604
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
302to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
30604Chemical etching
H01L 21/31111
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31105Etching inorganic layers
31111by chemical means
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • ZHU, Hongbin
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME
(FR) DISPOSITIFS DE MÉMOIRE TRIDIMENSIONNELS ET LEURS PROCÉDÉS DE FORMATION
Abstract
(EN) A 3D memory device (100) includes a substrate (102), a gate electrode (104) having a two-sided staircase shape above the substrate (102), a blocking layer (106) on the gate electrode (104), a plurality of discrete charge trapping layers (108a, 108b, 108c) each extending laterally on the blocking layer (106), a tunneling layer (110) on the charge trapping layers (108a, 108b, 108c), and a plurality of discrete channel layers (112a, 112b, 112c) each extending laterally on the tunneling layer (110). The charge trapping layers (108a, 108b, 108c) are disposed corresponding to stairs of the two-sided staircase shape of the gate electrode (104), respectively. The channel layers (112a, 112b, 112c) are disposed corresponding to the stairs of the two-sided staircase shape, respectively.
(FR) Dispositif de mémoire 3D (100) comprenant un substrat (102), une électrode de grille (104) ayant une forme d'escalier bilatéral au-dessus du substrat (102), une couche de blocage (106) sur l'électrode de grille (104), une pluralité de couches de piégeage de charge distinctes (108a, 108b, 108c) s'étendant chacune latéralement sur la couche de blocage (106), une couche de tunnellisation (110) sur les couches de piégeage de charge (108a, 108b, 108c), et une pluralité de couches de canal distinctes (112a, 112b, 112c) s'étendant chacune latéralement sur la couche de tunnellisation (110). Les couches de piégeage de charge (108a, 108b, 108c) sont disposées en correspondance avec les marches de la forme d'escalier bilatéral de l'électrode de grille (104), respectivement. Les couches de canal (112a, 112b, 112c) sont disposées en correspondance avec les marches de la forme d'escalier bilatéral, respectivement.
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