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1. WO2021041445 - JOINT COMMAND DYNAMIC RANDOM ACCESS MEMORY (DRAM) APPARATUS AND METHODS

Publication Number WO/2021/041445
Publication Date 04.03.2021
International Application No. PCT/US2020/047850
International Filing Date 25.08.2020
IPC
G06F 12/02 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G06F 12/02
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
G11C 11/4093
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4093Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 11/4096
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
G11C 5/066
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
066Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
G11C 7/1012
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
1012Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
G11C 7/1018
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1015Read-write modes for single port memories, i.e. having either a random port or a serial port
1018Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
Applicants
  • RAMBUS INC. [US]/[US]
Inventors
  • PARTSCH, Torsten
Agents
  • KREISMAN, Lance
Priority Data
62/892,33827.08.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) JOINT COMMAND DYNAMIC RANDOM ACCESS MEMORY (DRAM) APPARATUS AND METHODS
(FR) PROCÉDÉS ET APPAREIL DE MÉMOIRE VIVE DYNAMIQUE (DRAM) À COMMANDE COMMUNE
Abstract
(EN)
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) dynamic random access memory (DRAM) device is disclosed. The IC DRAM device includes memory core circuitry organized into bank groups of storage cells, each bank group accessible via a corresponding bank group address. A command/address (C/A) interface receives C/A information defining a joint command. The joint command includes information specifying a first memory access operation, a first bank group address associated with the first memory access operation, and a second memory access operation to be automatically directed to the first bank group address.
(FR)
L'invention concerne des contrôleurs de mémoire, des dispositifs, des modules, des systèmes et des procédés associés. Selon un mode de réalisation, l'invention concerne un dispositif de mémoire vive dynamique (DRAM) à circuit intégré (IC). Le dispositif de DRAM à IC comprend un ensemble de circuits de noyau de mémoire organisés en groupes de banques de cellules de mémorisation, chaque groupe de banques étant accessible par l'intermédiaire d'une adresse de groupe de banques correspondante. Une interface de commande/adresse (C/A) reçoit des informations de C/A définissant une commande conjointe. La commande conjointe comprend des informations spécifiant une première opération d'accès à la mémoire, une première adresse de groupe de banques associée à la première opération d'accès à la mémoire, et une seconde opération d'accès à la mémoire devant être automatiquement dirigée vers la première adresse de groupe de banques.
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