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1. WO2021041084 - ERROR CORRECTION FOR CONTENT-ADDRESSABLE MEMORY

Publication Number WO/2021/041084
Publication Date 04.03.2021
International Application No. PCT/US2020/046784
International Filing Date 18.08.2020
IPC
G11C 15/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
G06F 11/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/04 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
CPC
G06F 11/076
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
0751Error or fault detection not based on redundancy
0754by exceeding limits
076by exceeding a count or rate limit, e.g. word- or bit count limit
G06F 11/102
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1012using codes or arrangements adapted for a specific type of error
102Error in check bits
G11C 11/409
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
G11C 15/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04using semiconductor elements
G11C 5/063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
G11C 7/1006
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • AKEL, Ameen, D.
  • EILERT, Sean, S.
Agents
  • HARRIS, Philip
Priority Data
16/553,73128.08.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ERROR CORRECTION FOR CONTENT-ADDRESSABLE MEMORY
(FR) CORRECTION D'ERREURS POUR MÉMOIRE ADRESSABLE PAR LE CONTENU
Abstract
(EN)
Methods, systems, and devices for error correction for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a separate column or array of memory cells within the CAM. The CAM may similarly segment a queried input bit vector and identify, for each resulting input subvector, whether a matching subvector is stored by the CAM. The CAM may identify a match for the input bit vector when the number of matching subvectors satisfies a threshold. The CAM may validate a match based on comparing a stored bit vector corresponding to the identified match to the input bit vector. The stored bit vector may undergo error correction and may be stored in the CAM or another memory array, such as a dynamic random access memory (DRAM) array.
(FR)
Des procédés, des systèmes, et des dispositifs de correction d’erreurs pour une mémoire adressable par le contenu (CAM) sont décrits. Une CAM peut stocker des vecteurs de bits sous la forme d'un ensemble de sous-vecteurs, chaque sous-vecteur étant stocké dans un aspect indépendant de la CAM, tel que dans une colonne ou un réseau séparé de cellules de mémoire à l'intérieur de la CAM. La CAM peut segmenter de manière similaire un vecteur de bits d'entrée interrogé et identifier, pour chaque sous-vecteur d'entrée résultant, si un sous-vecteur correspondant est stocké par la CAM. La CAM peut identifier une correspondance pour le vecteur de bits d'entrée lorsque le nombre de sous-vecteurs correspondants satisfait un seuil. La CAM peut valider une correspondance sur la base de la comparaison d'un vecteur de bits stocké correspondant à la correspondance identifiée avec le vecteur de bits d'entrée. Le vecteur de bits stocké peut subir une correction d'erreurs et peut être stocké dans la CAM ou un autre réseau de mémoire, tel qu'un réseau de mémoire vive dynamique (DRAM).
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